Linux Audio
Check our new training course
Embedded Linux Audio
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974
/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef GAUDI_BLOCKS_H_ #define GAUDI_BLOCKS_H_ #define mmNIC0_PHY0_BASE 0x0ull #define NIC0_PHY0_MAX_OFFSET 0x9F13 #define mmMME0_ACC_BASE 0x7FFC020000ull #define MME0_ACC_MAX_OFFSET 0x5C00 #define MME0_ACC_SECTION 0x20000 #define mmMME0_SBAB_BASE 0x7FFC040000ull #define MME0_SBAB_MAX_OFFSET 0x5800 #define MME0_SBAB_SECTION 0x1000 #define mmMME0_PRTN_BASE 0x7FFC041000ull #define MME0_PRTN_MAX_OFFSET 0x5000 #define MME0_PRTN_SECTION 0x1F000 #define mmMME0_CTRL_BASE 0x7FFC060000ull #define MME0_CTRL_MAX_OFFSET 0xDA80 #define MME0_CTRL_SECTION 0x8000 #define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull #define ARCH_MME0_CTRL_MAX_OFFSET 0x3400 #define ARCH_MME0_CTRL_SECTION 0x3400 #define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull #define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00 #define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull #define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull #define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00 #define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull #define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull #define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull #define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00 #define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull #define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull #define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull #define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400 #define ARCH_DESC_MME0_CTRL_SECTION 0x2340 #define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull #define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400 #define SHADOW_0_MME0_CTRL_SECTION 0x3400 #define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull #define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull #define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull #define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull #define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull #define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull #define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull #define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull #define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull #define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400 #define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400 #define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull #define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400 #define SHADOW_1_MME0_CTRL_SECTION 0x3400 #define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull #define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull #define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull #define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull #define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull #define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull #define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull #define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull #define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull #define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400 #define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400 #define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull #define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400 #define SHADOW_2_MME0_CTRL_SECTION 0x3400 #define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull #define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull #define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull #define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull #define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull #define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull #define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull #define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull #define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull #define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400 #define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400 #define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull #define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400 #define SHADOW_3_MME0_CTRL_SECTION 0x3400 #define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull #define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull #define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull #define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull #define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull #define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull #define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull #define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull #define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 #define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull #define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400 #define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC #define mmMME0_QM_BASE 0x7FFC068000ull #define MME0_QM_MAX_OFFSET 0xD040 #define MME0_QM_SECTION 0x38000 #define mmMME1_ACC_BASE 0x7FFC0A0000ull #define MME1_ACC_MAX_OFFSET 0x5C00 #define MME1_ACC_SECTION 0x20000 #define mmMME1_SBAB_BASE 0x7FFC0C0000ull #define MME1_SBAB_MAX_OFFSET 0x5800 #define MME1_SBAB_SECTION 0x1000 #define mmMME1_PRTN_BASE 0x7FFC0C1000ull #define MME1_PRTN_MAX_OFFSET 0x5000 #define MME1_PRTN_SECTION 0x1F000 #define mmMME1_CTRL_BASE 0x7FFC0E0000ull #define MME1_CTRL_MAX_OFFSET 0xDA80 #define MME1_CTRL_SECTION 0x8000 #define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull #define ARCH_MME1_CTRL_MAX_OFFSET 0x3400 #define ARCH_MME1_CTRL_SECTION 0x3400 #define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull #define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00 #define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull #define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull #define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00 #define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull #define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull #define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull #define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00 #define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull #define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull #define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull #define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400 #define ARCH_DESC_MME1_CTRL_SECTION 0x2340 #define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull #define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400 #define SHADOW_0_MME1_CTRL_SECTION 0x3400 #define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull #define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull #define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull #define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull #define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull #define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull #define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull #define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull #define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull #define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400 #define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400 #define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull #define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400 #define SHADOW_1_MME1_CTRL_SECTION 0x3400 #define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull #define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull #define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull #define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull #define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull #define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull #define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull #define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull #define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull #define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400 #define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400 #define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull #define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400 #define SHADOW_2_MME1_CTRL_SECTION 0x3400 #define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull #define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull #define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull #define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull #define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull #define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull #define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull #define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull #define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull #define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400 #define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400 #define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull #define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400 #define SHADOW_3_MME1_CTRL_SECTION 0x3400 #define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull #define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull #define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull #define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull #define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull #define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull #define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull #define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull #define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 #define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull #define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400 #define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC #define mmMME1_QM_BASE 0x7FFC0E8000ull #define MME1_QM_MAX_OFFSET 0xD040 #define MME1_QM_SECTION 0x38000 #define mmMME2_ACC_BASE 0x7FFC120000ull #define MME2_ACC_MAX_OFFSET 0x5C00 #define MME2_ACC_SECTION 0x20000 #define mmMME2_SBAB_BASE 0x7FFC140000ull #define MME2_SBAB_MAX_OFFSET 0x5800 #define MME2_SBAB_SECTION 0x1000 #define mmMME2_PRTN_BASE 0x7FFC141000ull #define MME2_PRTN_MAX_OFFSET 0x5000 #define MME2_PRTN_SECTION 0x1F000 #define mmMME2_CTRL_BASE 0x7FFC160000ull #define MME2_CTRL_MAX_OFFSET 0xDA80 #define MME2_CTRL_SECTION 0x8000 #define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull #define ARCH_MME2_CTRL_MAX_OFFSET 0x3400 #define ARCH_MME2_CTRL_SECTION 0x3400 #define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull #define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00 #define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull #define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull #define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00 #define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull #define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull #define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull #define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00 #define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull #define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull #define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull #define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400 #define ARCH_DESC_MME2_CTRL_SECTION 0x2340 #define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull #define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400 #define SHADOW_0_MME2_CTRL_SECTION 0x3400 #define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull #define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull #define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull #define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull #define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull #define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull #define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull #define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull #define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull #define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400 #define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400 #define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull #define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400 #define SHADOW_1_MME2_CTRL_SECTION 0x3400 #define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull #define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull #define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull #define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull #define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull #define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull #define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull #define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull #define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull #define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400 #define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400 #define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull #define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400 #define SHADOW_2_MME2_CTRL_SECTION 0x3400 #define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull #define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull #define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull #define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull #define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull #define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull #define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull #define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull #define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull #define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400 #define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400 #define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull #define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400 #define SHADOW_3_MME2_CTRL_SECTION 0x3400 #define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull #define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull #define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull #define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull #define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull #define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull #define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull #define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull #define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 #define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull #define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400 #define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC #define mmMME2_QM_BASE 0x7FFC168000ull #define MME2_QM_MAX_OFFSET 0xD040 #define MME2_QM_SECTION 0x38000 #define mmMME3_ACC_BASE 0x7FFC1A0000ull #define MME3_ACC_MAX_OFFSET 0x5C00 #define MME3_ACC_SECTION 0x20000 #define mmMME3_SBAB_BASE 0x7FFC1C0000ull #define MME3_SBAB_MAX_OFFSET 0x5800 #define MME3_SBAB_SECTION 0x1000 #define mmMME3_PRTN_BASE 0x7FFC1C1000ull #define MME3_PRTN_MAX_OFFSET 0x5000 #define MME3_PRTN_SECTION 0x1F000 #define mmMME3_CTRL_BASE 0x7FFC1E0000ull #define MME3_CTRL_MAX_OFFSET 0xDA80 #define MME3_CTRL_SECTION 0x8000 #define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull #define ARCH_MME3_CTRL_MAX_OFFSET 0x3400 #define ARCH_MME3_CTRL_SECTION 0x3400 #define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull #define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00 #define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull #define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull #define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00 #define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull #define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull #define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull #define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 #define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00 #define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull #define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull #define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull #define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400 #define ARCH_DESC_MME3_CTRL_SECTION 0x2340 #define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull #define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400 #define SHADOW_0_MME3_CTRL_SECTION 0x3400 #define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull #define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull #define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull #define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull #define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull #define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull #define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull #define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull #define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull #define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400 #define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400 #define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull #define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400 #define SHADOW_1_MME3_CTRL_SECTION 0x3400 #define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull #define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull #define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull #define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull #define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull #define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull #define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull #define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull #define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull #define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400 #define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400 #define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull #define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400 #define SHADOW_2_MME3_CTRL_SECTION 0x3400 #define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull #define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull #define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull #define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull #define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull #define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull #define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull #define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull #define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull #define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400 #define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400 #define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull #define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400 #define SHADOW_3_MME3_CTRL_SECTION 0x3400 #define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull #define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull #define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull #define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull #define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull #define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull #define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 #define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00 #define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull #define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull #define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 #define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 #define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull #define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400 #define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC #define mmMME3_QM_BASE 0x7FFC1E8000ull #define MME3_QM_MAX_OFFSET 0xD040 #define MME3_QM_SECTION 0x18000 #define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull #define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X0_BANK_SECTION 0x1000 #define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull #define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X0_RTR_SECTION 0x7000 #define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull #define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X1_BANK_SECTION 0x1000 #define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull #define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X1_RTR_SECTION 0x7000 #define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull #define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X2_BANK_SECTION 0x1000 #define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull #define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X2_RTR_SECTION 0x7000 #define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull #define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X3_BANK_SECTION 0x1000 #define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull #define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X3_RTR_SECTION 0x7000 #define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull #define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X4_BANK_SECTION 0x1000 #define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull #define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X4_RTR_SECTION 0x7000 #define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull #define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X5_BANK_SECTION 0x1000 #define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull #define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X5_RTR_SECTION 0x7000 #define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull #define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X6_BANK_SECTION 0x1000 #define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull #define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X6_RTR_SECTION 0x7000 #define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull #define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000 #define SRAM_Y0_X7_BANK_SECTION 0x1000 #define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull #define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340 #define SRAM_Y0_X7_RTR_SECTION 0x7000 #define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull #define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X0_BANK_SECTION 0x1000 #define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull #define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X0_RTR_SECTION 0x7000 #define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull #define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X1_BANK_SECTION 0x1000 #define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull #define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X1_RTR_SECTION 0x7000 #define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull #define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X2_BANK_SECTION 0x1000 #define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull #define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X2_RTR_SECTION 0x7000 #define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull #define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X3_BANK_SECTION 0x1000 #define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull #define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X3_RTR_SECTION 0x7000 #define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull #define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X4_BANK_SECTION 0x1000 #define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull #define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X4_RTR_SECTION 0x7000 #define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull #define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X5_BANK_SECTION 0x1000 #define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull #define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X5_RTR_SECTION 0x7000 #define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull #define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X6_BANK_SECTION 0x1000 #define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull #define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X6_RTR_SECTION 0x7000 #define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull #define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000 #define SRAM_Y1_X7_BANK_SECTION 0x1000 #define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull #define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340 #define SRAM_Y1_X7_RTR_SECTION 0x7000 #define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull #define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X0_BANK_SECTION 0x1000 #define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull #define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X0_RTR_SECTION 0x7000 #define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull #define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X1_BANK_SECTION 0x1000 #define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull #define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X1_RTR_SECTION 0x7000 #define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull #define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X2_BANK_SECTION 0x1000 #define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull #define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X2_RTR_SECTION 0x7000 #define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull #define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X3_BANK_SECTION 0x1000 #define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull #define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X3_RTR_SECTION 0x7000 #define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull #define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X4_BANK_SECTION 0x1000 #define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull #define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X4_RTR_SECTION 0x7000 #define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull #define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X5_BANK_SECTION 0x1000 #define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull #define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X5_RTR_SECTION 0x7000 #define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull #define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X6_BANK_SECTION 0x1000 #define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull #define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X6_RTR_SECTION 0x7000 #define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull #define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000 #define SRAM_Y2_X7_BANK_SECTION 0x1000 #define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull #define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340 #define SRAM_Y2_X7_RTR_SECTION 0x7000 #define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull #define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X0_BANK_SECTION 0x1000 #define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull #define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X0_RTR_SECTION 0x7000 #define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull #define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X1_BANK_SECTION 0x1000 #define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull #define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X1_RTR_SECTION 0x7000 #define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull #define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X2_BANK_SECTION 0x1000 #define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull #define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X2_RTR_SECTION 0x7000 #define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull #define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X3_BANK_SECTION 0x1000 #define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull #define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X3_RTR_SECTION 0x7000 #define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull #define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X4_BANK_SECTION 0x1000 #define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull #define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X4_RTR_SECTION 0x7000 #define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull #define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X5_BANK_SECTION 0x1000 #define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull #define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X5_RTR_SECTION 0x7000 #define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull #define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X6_BANK_SECTION 0x1000 #define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull #define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X6_RTR_SECTION 0x7000 #define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull #define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000 #define SRAM_Y3_X7_BANK_SECTION 0x1000 #define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull #define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340 #define SRAM_Y3_X7_RTR_SECTION 0x7000 #define mmSIF_RTR_0_BASE 0x7FFC300000ull #define SIF_RTR_0_MAX_OFFSET 0x6500 #define SIF_RTR_0_SECTION 0x6000 #define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull #define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_0_SECTION 0xA000 #define mmSIF_RTR_1_BASE 0x7FFC310000ull #define SIF_RTR_1_MAX_OFFSET 0x6500 #define SIF_RTR_1_SECTION 0x6000 #define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull #define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_1_SECTION 0xA000 #define mmSIF_RTR_2_BASE 0x7FFC320000ull #define SIF_RTR_2_MAX_OFFSET 0x6500 #define SIF_RTR_2_SECTION 0x6000 #define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull #define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_2_SECTION 0xA000 #define mmSIF_RTR_3_BASE 0x7FFC330000ull #define SIF_RTR_3_MAX_OFFSET 0x6500 #define SIF_RTR_3_SECTION 0x6000 #define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull #define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_3_SECTION 0xA000 #define mmSIF_RTR_4_BASE 0x7FFC340000ull #define SIF_RTR_4_MAX_OFFSET 0x6500 #define SIF_RTR_4_SECTION 0x6000 #define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull #define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_4_SECTION 0xA000 #define mmSIF_RTR_5_BASE 0x7FFC350000ull #define SIF_RTR_5_MAX_OFFSET 0x6500 #define SIF_RTR_5_SECTION 0x6000 #define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull #define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_5_SECTION 0xA000 #define mmSIF_RTR_6_BASE 0x7FFC360000ull #define SIF_RTR_6_MAX_OFFSET 0x6500 #define SIF_RTR_6_SECTION 0x6000 #define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull #define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_6_SECTION 0xA000 #define mmSIF_RTR_7_BASE 0x7FFC370000ull #define SIF_RTR_7_MAX_OFFSET 0x6500 #define SIF_RTR_7_SECTION 0x6000 #define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull #define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 #define SIF_RTR_CTRL_7_SECTION 0xA000 #define mmNIF_RTR_0_BASE 0x7FFC380000ull #define NIF_RTR_0_MAX_OFFSET 0x6500 #define NIF_RTR_0_SECTION 0x6000 #define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull #define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_0_SECTION 0xA000 #define mmNIF_RTR_1_BASE 0x7FFC390000ull #define NIF_RTR_1_MAX_OFFSET 0x6500 #define NIF_RTR_1_SECTION 0x6000 #define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull #define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_1_SECTION 0xA000 #define mmNIF_RTR_2_BASE 0x7FFC3A0000ull #define NIF_RTR_2_MAX_OFFSET 0x6500 #define NIF_RTR_2_SECTION 0x6000 #define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull #define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_2_SECTION 0xA000 #define mmNIF_RTR_3_BASE 0x7FFC3B0000ull #define NIF_RTR_3_MAX_OFFSET 0x6500 #define NIF_RTR_3_SECTION 0x6000 #define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull #define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_3_SECTION 0xA000 #define mmNIF_RTR_4_BASE 0x7FFC3C0000ull #define NIF_RTR_4_MAX_OFFSET 0x6500 #define NIF_RTR_4_SECTION 0x6000 #define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull #define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_4_SECTION 0xA000 #define mmNIF_RTR_5_BASE 0x7FFC3D0000ull #define NIF_RTR_5_MAX_OFFSET 0x6500 #define NIF_RTR_5_SECTION 0x6000 #define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull #define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_5_SECTION 0xA000 #define mmNIF_RTR_6_BASE 0x7FFC3E0000ull #define NIF_RTR_6_MAX_OFFSET 0x6500 #define NIF_RTR_6_SECTION 0x6000 #define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull #define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_6_SECTION 0xA000 #define mmNIF_RTR_7_BASE 0x7FFC3F0000ull #define NIF_RTR_7_MAX_OFFSET 0x6500 #define NIF_RTR_7_SECTION 0x6000 #define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull #define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 #define NIF_RTR_CTRL_7_SECTION 0x4B000 #define mmCPU_CA53_CFG_BASE 0x7FFC441000ull #define CPU_CA53_CFG_MAX_OFFSET 0x2180 #define CPU_CA53_CFG_SECTION 0x1000 #define mmCPU_IF_BASE 0x7FFC442000ull #define CPU_IF_MAX_OFFSET 0x43C0 #define CPU_IF_SECTION 0x2000 #define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull #define CPU_TIMESTAMP_MAX_OFFSET 0x1000 #define CPU_TIMESTAMP_SECTION 0x3C000 #define mmDMA_IF_W_S_BASE 0x7FFC480000ull #define DMA_IF_W_S_MAX_OFFSET 0x8380 #define DMA_IF_W_S_SECTION 0x1000 #define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull #define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00 #define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000 #define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull #define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00 #define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000 #define mmDMA_W_PLL_BASE 0x7FFC487000ull #define DMA_W_PLL_MAX_OFFSET 0x5200 #define DMA_W_PLL_SECTION 0x1000 #define mmIF_W_PLL_BASE 0x7FFC488000ull #define IF_W_PLL_MAX_OFFSET 0x5200 #define IF_W_PLL_SECTION 0x1000 #define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull #define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500 #define DMA_IF_W_S_DOWN_SECTION 0x7000 #define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull #define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00 #define SYNC_MNGR_GLBL_W_S_SECTION 0x1000 #define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull #define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00 #define SYNC_MNGR_OBJS_W_S_SECTION 0xF000 #define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull #define DMA_IF_E_S_MAX_OFFSET 0x8380 #define DMA_IF_E_S_SECTION 0x1000 #define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull #define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00 #define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000 #define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull #define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00 #define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000 #define mmIF_E_PLL_BASE 0x7FFC4A7000ull #define IF_E_PLL_MAX_OFFSET 0x5200 #define IF_E_PLL_SECTION 0x1000 #define mmDMA_E_PLL_BASE 0x7FFC4A8000ull #define DMA_E_PLL_MAX_OFFSET 0x5200 #define DMA_E_PLL_SECTION 0x1000 #define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull #define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500 #define DMA_IF_E_S_DOWN_SECTION 0x7000 #define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull #define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00 #define SYNC_MNGR_GLBL_E_S_SECTION 0x1000 #define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull #define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00 #define SYNC_MNGR_OBJS_E_S_SECTION 0xF000 #define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull #define DMA_IF_W_N_MAX_OFFSET 0x8380 #define DMA_IF_W_N_SECTION 0x1000 #define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull #define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00 #define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000 #define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull #define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00 #define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000 #define mmMESH_W_PLL_BASE 0x7FFC4C7000ull #define MESH_W_PLL_MAX_OFFSET 0x5200 #define MESH_W_PLL_SECTION 0x1000 #define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull #define SRAM_W_PLL_MAX_OFFSET 0x5200 #define SRAM_W_PLL_SECTION 0x1000 #define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull #define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500 #define DMA_IF_W_N_DOWN_SECTION 0x7000 #define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull #define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00 #define SYNC_MNGR_GLBL_W_N_SECTION 0x1000 #define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull #define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00 #define SYNC_MNGR_OBJS_W_N_SECTION 0xF000 #define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull #define DMA_IF_E_N_MAX_OFFSET 0x8380 #define DMA_IF_E_N_SECTION 0x1000 #define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull #define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00 #define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000 #define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull #define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00 #define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000 #define mmMESH_E_PLL_BASE 0x7FFC4E7000ull #define MESH_E_PLL_MAX_OFFSET 0x5200 #define MESH_E_PLL_SECTION 0x1000 #define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull #define SRAM_E_PLL_MAX_OFFSET 0x5200 #define SRAM_E_PLL_SECTION 0x1000 #define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull #define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500 #define DMA_IF_E_N_DOWN_SECTION 0x7000 #define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull #define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00 #define SYNC_MNGR_GLBL_E_N_SECTION 0x1000 #define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull #define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00 #define SYNC_MNGR_OBJS_E_N_SECTION 0xF000 #define mmDMA0_CORE_BASE 0x7FFC500000ull #define DMA0_CORE_MAX_OFFSET 0x23C0 #define DMA0_CORE_SECTION 0x8000 #define mmDMA0_QM_BASE 0x7FFC508000ull #define DMA0_QM_MAX_OFFSET 0xD040 #define DMA0_QM_SECTION 0x18000 #define mmDMA1_CORE_BASE 0x7FFC520000ull #define DMA1_CORE_MAX_OFFSET 0x23C0 #define DMA1_CORE_SECTION 0x8000 #define mmDMA1_QM_BASE 0x7FFC528000ull #define DMA1_QM_MAX_OFFSET 0xD040 #define DMA1_QM_SECTION 0x18000 #define mmDMA2_CORE_BASE 0x7FFC540000ull #define DMA2_CORE_MAX_OFFSET 0x23C0 #define DMA2_CORE_SECTION 0x8000 #define mmDMA2_QM_BASE 0x7FFC548000ull #define DMA2_QM_MAX_OFFSET 0xD040 #define DMA2_QM_SECTION 0x18000 #define mmDMA3_CORE_BASE 0x7FFC560000ull #define DMA3_CORE_MAX_OFFSET 0x23C0 #define DMA3_CORE_SECTION 0x8000 #define mmDMA3_QM_BASE 0x7FFC568000ull #define DMA3_QM_MAX_OFFSET 0xD040 #define DMA3_QM_SECTION 0x18000 #define mmDMA4_CORE_BASE 0x7FFC580000ull #define DMA4_CORE_MAX_OFFSET 0x23C0 #define DMA4_CORE_SECTION 0x8000 #define mmDMA4_QM_BASE 0x7FFC588000ull #define DMA4_QM_MAX_OFFSET 0xD040 #define DMA4_QM_SECTION 0x18000 #define mmDMA5_CORE_BASE 0x7FFC5A0000ull #define DMA5_CORE_MAX_OFFSET 0x23C0 #define DMA5_CORE_SECTION 0x8000 #define mmDMA5_QM_BASE 0x7FFC5A8000ull #define DMA5_QM_MAX_OFFSET 0xD040 #define DMA5_QM_SECTION 0x18000 #define mmDMA6_CORE_BASE 0x7FFC5C0000ull #define DMA6_CORE_MAX_OFFSET 0x23C0 #define DMA6_CORE_SECTION 0x8000 #define mmDMA6_QM_BASE 0x7FFC5C8000ull #define DMA6_QM_MAX_OFFSET 0xD040 #define DMA6_QM_SECTION 0x18000 #define mmDMA7_CORE_BASE 0x7FFC5E0000ull #define DMA7_CORE_MAX_OFFSET 0x23C0 #define DMA7_CORE_SECTION 0x8000 #define mmDMA7_QM_BASE 0x7FFC5E8000ull #define DMA7_QM_MAX_OFFSET 0xD040 #define DMA7_QM_SECTION 0x18000 #define mmHBM0_BASE 0x7FFC600000ull #define HBM0_MAX_OFFSET 0x8F58 #define HBM0_SECTION 0x80000 #define mmHBM1_BASE 0x7FFC680000ull #define HBM1_MAX_OFFSET 0x8F58 #define HBM1_SECTION 0x80000 #define mmHBM2_BASE 0x7FFC700000ull #define HBM2_MAX_OFFSET 0x8F58 #define HBM2_SECTION 0x80000 #define mmHBM3_BASE 0x7FFC780000ull #define HBM3_MAX_OFFSET 0x8F58 #define HBM3_SECTION 0x80000 #define mmGIC_BASE 0x7FFC800000ull #define GIC_MAX_OFFSET 0x10000 #define GIC_SECTION 0x401000 #define mmPCIE_WRAP_BASE 0x7FFCC01000ull #define PCIE_WRAP_MAX_OFFSET 0xDF00 #define PCIE_WRAP_SECTION 0x1000 #define mmPCIE_DBI_BASE 0x7FFCC02000ull #define PCIE_DBI_MAX_OFFSET 0xC040 #define PCIE_DBI_SECTION 0x2000 #define mmPCIE_CORE_BASE 0x7FFCC04000ull #define PCIE_CORE_MAX_OFFSET 0x9BC0 #define PCIE_CORE_SECTION 0x3000 #define mmPCIE_AUX_BASE 0x7FFCC07000ull #define PCIE_AUX_MAX_OFFSET 0x9C40 #define PCIE_AUX_SECTION 0x9000 #define mmPCIE_PHY_BASE 0x7FFCC10000ull #define PCIE_PHY_MAX_OFFSET 0x9640 #define PCIE_PHY_SECTION 0x1000 #define mmMMU_UP_BASE 0x7FFCC11000ull #define MMU_UP_MAX_OFFSET 0x7000 #define MMU_UP_SECTION 0x1000 #define mmSTLB_BASE 0x7FFCC12000ull #define STLB_MAX_OFFSET 0x8800 #define STLB_SECTION 0x1000 #define mmPCIE_MSI_BASE 0x7FFCC13000ull #define PCIE_MSI_MAX_OFFSET 0x8000 #define PCIE_MSI_SECTION 0x2D000 #define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull #define PSOC_I2C_M0_MAX_OFFSET 0x1000 #define PSOC_I2C_M0_SECTION 0x1000 #define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull #define PSOC_I2C_M1_MAX_OFFSET 0x1000 #define PSOC_I2C_M1_SECTION 0x1000 #define mmPSOC_I2C_S_BASE 0x7FFCC42000ull #define PSOC_I2C_S_MAX_OFFSET 0x1000 #define PSOC_I2C_S_SECTION 0x1000 #define mmPSOC_SPI_BASE 0x7FFCC43000ull #define PSOC_SPI_MAX_OFFSET 0x1000 #define PSOC_SPI_SECTION 0x2000 #define mmPSOC_UART_0_BASE 0x7FFCC45000ull #define PSOC_UART_0_MAX_OFFSET 0x1000 #define PSOC_UART_0_SECTION 0x1000 #define mmPSOC_UART_1_BASE 0x7FFCC46000ull #define PSOC_UART_1_MAX_OFFSET 0x1000 #define PSOC_UART_1_SECTION 0x1000 #define mmPSOC_TIMER_BASE 0x7FFCC47000ull #define PSOC_TIMER_MAX_OFFSET 0x1000 #define PSOC_TIMER_SECTION 0x1000 #define mmPSOC_WDOG_BASE 0x7FFCC48000ull #define PSOC_WDOG_MAX_OFFSET 0x1000 #define PSOC_WDOG_SECTION 0x1000 #define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull #define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 #define PSOC_TIMESTAMP_SECTION 0x1000 #define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull #define PSOC_EFUSE_MAX_OFFSET 0x3040 #define PSOC_EFUSE_SECTION 0x1000 #define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull #define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80 #define PSOC_GLOBAL_CONF_SECTION 0x1000 #define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull #define PSOC_GPIO0_MAX_OFFSET 0x1000 #define PSOC_GPIO0_SECTION 0x1000 #define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull #define PSOC_GPIO1_MAX_OFFSET 0x1000 #define PSOC_GPIO1_SECTION 0x1000 #define mmPSOC_BTL_BASE 0x7FFCC4E000ull #define PSOC_BTL_MAX_OFFSET 0x1480 #define PSOC_BTL_SECTION 0x1000 #define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull #define PSOC_CS_TRACE_MAX_OFFSET 0x1680 #define PSOC_CS_TRACE_SECTION 0x1000 #define mmPSOC_GPIO2_BASE 0x7FFCC50000ull #define PSOC_GPIO2_MAX_OFFSET 0x1000 #define PSOC_GPIO2_SECTION 0x1000 #define mmPSOC_GPIO3_BASE 0x7FFCC51000ull #define PSOC_GPIO3_MAX_OFFSET 0x1000 #define PSOC_GPIO3_SECTION 0x1000 #define mmPSOC_GPIO4_BASE 0x7FFCC52000ull #define PSOC_GPIO4_MAX_OFFSET 0x1000 #define PSOC_GPIO4_SECTION 0x1000 #define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull #define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040 #define PSOC_DFT_EFUSE_SECTION 0x1000 #define mmPSOC_RPM_0_BASE 0x7FFCC54000ull #define PSOC_RPM_0_MAX_OFFSET 0x8800 #define PSOC_RPM_0_SECTION 0x1000 #define mmPSOC_RPM_1_BASE 0x7FFCC55000ull #define PSOC_RPM_1_MAX_OFFSET 0x8800 #define PSOC_RPM_1_SECTION 0x1000 #define mmPSOC_RPM_2_BASE 0x7FFCC56000ull #define PSOC_RPM_2_MAX_OFFSET 0x8800 #define PSOC_RPM_2_SECTION 0x1000 #define mmPSOC_RPM_3_BASE 0x7FFCC57000ull #define PSOC_RPM_3_MAX_OFFSET 0x8800 #define PSOC_RPM_3_SECTION 0x19000 #define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull #define PSOC_CPU_PLL_MAX_OFFSET 0x5200 #define PSOC_CPU_PLL_SECTION 0x1000 #define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull #define PSOC_MME_PLL_MAX_OFFSET 0x5200 #define PSOC_MME_PLL_SECTION 0x1000 #define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull #define PSOC_PCI_PLL_MAX_OFFSET 0x5200 #define PSOC_PCI_PLL_SECTION 0x1000 #define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull #define PSOC_TPC_PLL_MAX_OFFSET 0x5200 #define PSOC_TPC_PLL_SECTION 0x1000 #define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull #define PSOC_HBM_PLL_MAX_OFFSET 0x5200 #define PSOC_HBM_PLL_SECTION 0x1000 #define mmPSOC_PM_BASE 0x7FFCC75000ull #define PSOC_PM_MAX_OFFSET 0x1F00 #define PSOC_PM_SECTION 0x1000 #define mmPSOC_TS_BASE 0x7FFCC76000ull #define PSOC_TS_MAX_OFFSET 0xE640 #define PSOC_TS_SECTION 0x2000 #define mmPSOC_PWM0_BASE 0x7FFCC78000ull #define PSOC_PWM0_MAX_OFFSET 0x5800 #define PSOC_PWM0_SECTION 0x1000 #define mmPSOC_PWM1_BASE 0x7FFCC79000ull #define PSOC_PWM1_MAX_OFFSET 0x5800 #define PSOC_PWM1_SECTION 0x1000 #define mmPSOC_PWM2_BASE 0x7FFCC7A000ull #define PSOC_PWM2_MAX_OFFSET 0x5800 #define PSOC_PWM2_SECTION 0x1000 #define mmPSOC_PWM3_BASE 0x7FFCC7B000ull #define PSOC_PWM3_MAX_OFFSET 0x5800 #define PSOC_PWM3_SECTION 0x1000 #define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull #define PSOC_GPIO5_MAX_OFFSET 0x1000 #define PSOC_GPIO5_SECTION 0x1000 #define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull #define PSOC_GPIO6_MAX_OFFSET 0x1000 #define PSOC_GPIO6_SECTION 0x3000 #define mmPCIE_PMA_0_BASE 0x7FFCC80000ull #define PCIE_PMA_0_MAX_OFFSET 0x10003 #define PCIE_PMA_0_SECTION 0x10000 #define mmPCIE_PMA_1_BASE 0x7FFCC90000ull #define PCIE_PMA_1_MAX_OFFSET 0x10003 #define PCIE_PMA_1_SECTION 0x10000 #define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull #define PCIE_PMA_2_MAX_OFFSET 0x10003 #define PCIE_PMA_2_SECTION 0x10000 #define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull #define PCIE_PMA_3_MAX_OFFSET 0x10003 #define PCIE_PMA_3_SECTION 0x10000 #define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull #define NIC0_MAC_CH0_MAX_OFFSET 0x8400 #define NIC0_MAC_CH0_SECTION 0x1000 #define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull #define NIC0_MAC_CH1_MAX_OFFSET 0x8400 #define NIC0_MAC_CH1_SECTION 0x1000 #define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull #define NIC0_MAC_CH2_MAX_OFFSET 0x8400 #define NIC0_MAC_CH2_SECTION 0x1000 #define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull #define NIC0_MAC_CH3_MAX_OFFSET 0x8400 #define NIC0_MAC_CH3_SECTION 0x1000 #define mmNIC0_STAT_BASE 0x7FFCCC4000ull #define NIC0_STAT_MAX_OFFSET 0x4D00 #define NIC0_STAT_SECTION 0x1000 #define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull #define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380 #define NIC0_MAC_XPCS91_SECTION 0x3000 #define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull #define NIC0_MAC_CORE_MAX_OFFSET 0x5400 #define NIC0_MAC_CORE_SECTION 0x1000 #define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull #define NIC0_MAC_AUX_MAX_OFFSET 0x3000 #define NIC0_MAC_AUX_SECTION 0xF000 #define mmNIC0_PHY_BASE 0x7FFCCD8000ull #define NIC0_PHY_MAX_OFFSET 0x3400 #define NIC0_PHY_SECTION 0x8000 #define mmNIC0_QM0_BASE 0x7FFCCE0000ull #define NIC0_QM0_MAX_OFFSET 0xD040 #define NIC0_QM0_SECTION 0x2000 #define mmNIC0_QM1_BASE 0x7FFCCE2000ull #define NIC0_QM1_MAX_OFFSET 0xD040 #define NIC0_QM1_SECTION 0x2000 #define mmNIC0_QPC0_BASE 0x7FFCCE4000ull #define NIC0_QPC0_MAX_OFFSET 0x7140 #define NIC0_QPC0_SECTION 0x1000 #define mmNIC0_QPC1_BASE 0x7FFCCE5000ull #define NIC0_QPC1_MAX_OFFSET 0x7140 #define NIC0_QPC1_SECTION 0x3000 #define mmNIC0_RXB_BASE 0x7FFCCE8000ull #define NIC0_RXB_MAX_OFFSET 0x6040 #define NIC0_RXB_SECTION 0x1000 #define mmNIC0_RXE0_BASE 0x7FFCCE9000ull #define NIC0_RXE0_MAX_OFFSET 0x2FC0 #define NIC0_RXE0_SECTION 0x1000 #define mmNIC0_RXE1_BASE 0x7FFCCEA000ull #define NIC0_RXE1_MAX_OFFSET 0x2FC0 #define NIC0_RXE1_SECTION 0x1000 #define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull #define NIC0_RX_GW_MAX_OFFSET 0x4540 #define NIC0_RX_GW_SECTION 0x5000 #define mmNIC0_TXS0_BASE 0x7FFCCF0000ull #define NIC0_TXS0_MAX_OFFSET 0x19C0 #define NIC0_TXS0_SECTION 0x1000 #define mmNIC0_TXS1_BASE 0x7FFCCF1000ull #define NIC0_TXS1_MAX_OFFSET 0x19C0 #define NIC0_TXS1_SECTION 0x1000 #define mmNIC0_TXE0_BASE 0x7FFCCF2000ull #define NIC0_TXE0_MAX_OFFSET 0x2040 #define NIC0_TXE0_SECTION 0x1000 #define mmNIC0_TXE1_BASE 0x7FFCCF3000ull #define NIC0_TXE1_MAX_OFFSET 0x2040 #define NIC0_TXE1_SECTION 0x1000 #define mmNIC0_TXB_BASE 0x7FFCCF4000ull #define NIC0_TXB_MAX_OFFSET 0xD400 #define NIC0_TXB_SECTION 0x1000 #define mmNIC0_TMR_BASE 0x7FFCCF5000ull #define NIC0_TMR_MAX_OFFSET 0x1600 #define NIC0_TMR_SECTION 0x1000 #define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull #define NIC0_TX_GW_MAX_OFFSET 0x1400 #define NIC0_TX_GW_SECTION 0x2000 #define mmNIC0_TS_BASE 0x7FFCCF8000ull #define NIC0_TS_MAX_OFFSET 0xE640 #define NIC0_TS_SECTION 0x1000 #define mmNIC0_PLL_BASE 0x7FFCCF9000ull #define NIC0_PLL_MAX_OFFSET 0x5200 #define NIC0_PLL_SECTION 0x1000 #define mmNIC0_PM_BASE 0x7FFCCFA000ull #define NIC0_PM_MAX_OFFSET 0x1F00 #define NIC0_PM_SECTION 0x6000 #define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull #define NIC1_MAC_CH0_MAX_OFFSET 0x8400 #define NIC1_MAC_CH0_SECTION 0x1000 #define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull #define NIC1_MAC_CH1_MAX_OFFSET 0x8400 #define NIC1_MAC_CH1_SECTION 0x1000 #define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull #define NIC1_MAC_CH2_MAX_OFFSET 0x8400 #define NIC1_MAC_CH2_SECTION 0x1000 #define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull #define NIC1_MAC_CH3_MAX_OFFSET 0x8400 #define NIC1_MAC_CH3_SECTION 0x1000 #define mmNIC1_STAT_BASE 0x7FFCD04000ull #define NIC1_STAT_MAX_OFFSET 0x4D00 #define NIC1_STAT_SECTION 0x1000 #define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull #define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380 #define NIC1_MAC_XPCS91_SECTION 0x3000 #define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull #define NIC1_MAC_CORE_MAX_OFFSET 0x5400 #define NIC1_MAC_CORE_SECTION 0x1000 #define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull #define NIC1_MAC_AUX_MAX_OFFSET 0x3000 #define NIC1_MAC_AUX_SECTION 0xF000 #define mmNIC1_PHY_BASE 0x7FFCD18000ull #define NIC1_PHY_MAX_OFFSET 0x3400 #define NIC1_PHY_SECTION 0x8000 #define mmNIC1_QM0_BASE 0x7FFCD20000ull #define NIC1_QM0_MAX_OFFSET 0xD040 #define NIC1_QM0_SECTION 0x2000 #define mmNIC1_QM1_BASE 0x7FFCD22000ull #define NIC1_QM1_MAX_OFFSET 0xD040 #define NIC1_QM1_SECTION 0x2000 #define mmNIC1_QPC0_BASE 0x7FFCD24000ull #define NIC1_QPC0_MAX_OFFSET 0x7140 #define NIC1_QPC0_SECTION 0x1000 #define mmNIC1_QPC1_BASE 0x7FFCD25000ull #define NIC1_QPC1_MAX_OFFSET 0x7140 #define NIC1_QPC1_SECTION 0x3000 #define mmNIC1_RXB_BASE 0x7FFCD28000ull #define NIC1_RXB_MAX_OFFSET 0x6040 #define NIC1_RXB_SECTION 0x1000 #define mmNIC1_RXE0_BASE 0x7FFCD29000ull #define NIC1_RXE0_MAX_OFFSET 0x2FC0 #define NIC1_RXE0_SECTION 0x1000 #define mmNIC1_RXE1_BASE 0x7FFCD2A000ull #define NIC1_RXE1_MAX_OFFSET 0x2FC0 #define NIC1_RXE1_SECTION 0x1000 #define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull #define NIC1_RX_GW_MAX_OFFSET 0x4540 #define NIC1_RX_GW_SECTION 0x5000 #define mmNIC1_TXS0_BASE 0x7FFCD30000ull #define NIC1_TXS0_MAX_OFFSET 0x19C0 #define NIC1_TXS0_SECTION 0x1000 #define mmNIC1_TXS1_BASE 0x7FFCD31000ull #define NIC1_TXS1_MAX_OFFSET 0x19C0 #define NIC1_TXS1_SECTION 0x1000 #define mmNIC1_TXE0_BASE 0x7FFCD32000ull #define NIC1_TXE0_MAX_OFFSET 0x2040 #define NIC1_TXE0_SECTION 0x1000 #define mmNIC1_TXE1_BASE 0x7FFCD33000ull #define NIC1_TXE1_MAX_OFFSET 0x2040 #define NIC1_TXE1_SECTION 0x1000 #define mmNIC1_TXB_BASE 0x7FFCD34000ull #define NIC1_TXB_MAX_OFFSET 0xD400 #define NIC1_TXB_SECTION 0x1000 #define mmNIC1_TMR_BASE 0x7FFCD35000ull #define NIC1_TMR_MAX_OFFSET 0x1600 #define NIC1_TMR_SECTION 0x1000 #define mmNIC1_TX_GW_BASE 0x7FFCD36000ull #define NIC1_TX_GW_MAX_OFFSET 0x1400 #define NIC1_TX_GW_SECTION 0x2000 #define mmNIC1_TS_BASE 0x7FFCD38000ull #define NIC1_TS_MAX_OFFSET 0xE640 #define NIC1_TS_SECTION 0x1000 #define mmNIC1_PLL_BASE 0x7FFCD39000ull #define NIC1_PLL_MAX_OFFSET 0x5200 #define NIC1_PLL_SECTION 0x1000 #define mmNIC1_PM_BASE 0x7FFCD3A000ull #define NIC1_PM_MAX_OFFSET 0x1F00 #define NIC1_PM_SECTION 0x6000 #define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull #define NIC2_MAC_CH0_MAX_OFFSET 0x8400 #define NIC2_MAC_CH0_SECTION 0x1000 #define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull #define NIC2_MAC_CH1_MAX_OFFSET 0x8400 #define NIC2_MAC_CH1_SECTION 0x1000 #define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull #define NIC2_MAC_CH2_MAX_OFFSET 0x8400 #define NIC2_MAC_CH2_SECTION 0x1000 #define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull #define NIC2_MAC_CH3_MAX_OFFSET 0x8400 #define NIC2_MAC_CH3_SECTION 0x1000 #define mmNIC2_STAT_BASE 0x7FFCD44000ull #define NIC2_STAT_MAX_OFFSET 0x4D00 #define NIC2_STAT_SECTION 0x1000 #define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull #define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380 #define NIC2_MAC_XPCS91_SECTION 0x3000 #define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull #define NIC2_MAC_CORE_MAX_OFFSET 0x5400 #define NIC2_MAC_CORE_SECTION 0x1000 #define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull #define NIC2_MAC_AUX_MAX_OFFSET 0x3000 #define NIC2_MAC_AUX_SECTION 0xF000 #define mmNIC2_PHY_BASE 0x7FFCD58000ull #define NIC2_PHY_MAX_OFFSET 0x3400 #define NIC2_PHY_SECTION 0x8000 #define mmNIC2_QM0_BASE 0x7FFCD60000ull #define NIC2_QM0_MAX_OFFSET 0xD040 #define NIC2_QM0_SECTION 0x2000 #define mmNIC2_QM1_BASE 0x7FFCD62000ull #define NIC2_QM1_MAX_OFFSET 0xD040 #define NIC2_QM1_SECTION 0x2000 #define mmNIC2_QPC0_BASE 0x7FFCD64000ull #define NIC2_QPC0_MAX_OFFSET 0x7140 #define NIC2_QPC0_SECTION 0x1000 #define mmNIC2_QPC1_BASE 0x7FFCD65000ull #define NIC2_QPC1_MAX_OFFSET 0x7140 #define NIC2_QPC1_SECTION 0x3000 #define mmNIC2_RXB_BASE 0x7FFCD68000ull #define NIC2_RXB_MAX_OFFSET 0x6040 #define NIC2_RXB_SECTION 0x1000 #define mmNIC2_RXE0_BASE 0x7FFCD69000ull #define NIC2_RXE0_MAX_OFFSET 0x2FC0 #define NIC2_RXE0_SECTION 0x1000 #define mmNIC2_RXE1_BASE 0x7FFCD6A000ull #define NIC2_RXE1_MAX_OFFSET 0x2FC0 #define NIC2_RXE1_SECTION 0x1000 #define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull #define NIC2_RX_GW_MAX_OFFSET 0x4540 #define NIC2_RX_GW_SECTION 0x5000 #define mmNIC2_TXS0_BASE 0x7FFCD70000ull #define NIC2_TXS0_MAX_OFFSET 0x19C0 #define NIC2_TXS0_SECTION 0x1000 #define mmNIC2_TXS1_BASE 0x7FFCD71000ull #define NIC2_TXS1_MAX_OFFSET 0x19C0 #define NIC2_TXS1_SECTION 0x1000 #define mmNIC2_TXE0_BASE 0x7FFCD72000ull #define NIC2_TXE0_MAX_OFFSET 0x2040 #define NIC2_TXE0_SECTION 0x1000 #define mmNIC2_TXE1_BASE 0x7FFCD73000ull #define NIC2_TXE1_MAX_OFFSET 0x2040 #define NIC2_TXE1_SECTION 0x1000 #define mmNIC2_TXB_BASE 0x7FFCD74000ull #define NIC2_TXB_MAX_OFFSET 0xD400 #define NIC2_TXB_SECTION 0x1000 #define mmNIC2_TMR_BASE 0x7FFCD75000ull #define NIC2_TMR_MAX_OFFSET 0x1600 #define NIC2_TMR_SECTION 0x1000 #define mmNIC2_TX_GW_BASE 0x7FFCD76000ull #define NIC2_TX_GW_MAX_OFFSET 0x1400 #define NIC2_TX_GW_SECTION 0x2000 #define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull #define NIC2_HBM_PLL_MAX_OFFSET 0x5200 #define NIC2_HBM_PLL_SECTION 0x1000 #define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull #define NIC2_MME_PLL_MAX_OFFSET 0x5200 #define NIC2_MME_PLL_SECTION 0x1000 #define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull #define NIC2_TPC_PLL_MAX_OFFSET 0x5200 #define NIC2_TPC_PLL_SECTION 0x6000 #define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull #define NIC3_MAC_CH0_MAX_OFFSET 0x8400 #define NIC3_MAC_CH0_SECTION 0x1000 #define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull #define NIC3_MAC_CH1_MAX_OFFSET 0x8400 #define NIC3_MAC_CH1_SECTION 0x1000 #define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull #define NIC3_MAC_CH2_MAX_OFFSET 0x8400 #define NIC3_MAC_CH2_SECTION 0x1000 #define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull #define NIC3_MAC_CH3_MAX_OFFSET 0x8400 #define NIC3_MAC_CH3_SECTION 0x1000 #define mmNIC3_STAT_BASE 0x7FFCD84000ull #define NIC3_STAT_MAX_OFFSET 0x4D00 #define NIC3_STAT_SECTION 0x1000 #define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull #define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380 #define NIC3_MAC_XPCS91_SECTION 0x3000 #define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull #define NIC3_MAC_CORE_MAX_OFFSET 0x5400 #define NIC3_MAC_CORE_SECTION 0x1000 #define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull #define NIC3_MAC_AUX_MAX_OFFSET 0x3000 #define NIC3_MAC_AUX_SECTION 0xF000 #define mmNIC3_PHY_BASE 0x7FFCD98000ull #define NIC3_PHY_MAX_OFFSET 0x3400 #define NIC3_PHY_SECTION 0x8000 #define mmNIC3_QM0_BASE 0x7FFCDA0000ull #define NIC3_QM0_MAX_OFFSET 0xD040 #define NIC3_QM0_SECTION 0x2000 #define mmNIC3_QM1_BASE 0x7FFCDA2000ull #define NIC3_QM1_MAX_OFFSET 0xD040 #define NIC3_QM1_SECTION 0x2000 #define mmNIC3_QPC0_BASE 0x7FFCDA4000ull #define NIC3_QPC0_MAX_OFFSET 0x7140 #define NIC3_QPC0_SECTION 0x1000 #define mmNIC3_QPC1_BASE 0x7FFCDA5000ull #define NIC3_QPC1_MAX_OFFSET 0x7140 #define NIC3_QPC1_SECTION 0x3000 #define mmNIC3_RXB_BASE 0x7FFCDA8000ull #define NIC3_RXB_MAX_OFFSET 0x6040 #define NIC3_RXB_SECTION 0x1000 #define mmNIC3_RXE0_BASE 0x7FFCDA9000ull #define NIC3_RXE0_MAX_OFFSET 0x2FC0 #define NIC3_RXE0_SECTION 0x1000 #define mmNIC3_RXE1_BASE 0x7FFCDAA000ull #define NIC3_RXE1_MAX_OFFSET 0x2FC0 #define NIC3_RXE1_SECTION 0x1000 #define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull #define NIC3_RX_GW_MAX_OFFSET 0x4540 #define NIC3_RX_GW_SECTION 0x5000 #define mmNIC3_TXS0_BASE 0x7FFCDB0000ull #define NIC3_TXS0_MAX_OFFSET 0x19C0 #define NIC3_TXS0_SECTION 0x1000 #define mmNIC3_TXS1_BASE 0x7FFCDB1000ull #define NIC3_TXS1_MAX_OFFSET 0x19C0 #define NIC3_TXS1_SECTION 0x1000 #define mmNIC3_TXE0_BASE 0x7FFCDB2000ull #define NIC3_TXE0_MAX_OFFSET 0x2040 #define NIC3_TXE0_SECTION 0x1000 #define mmNIC3_TXE1_BASE 0x7FFCDB3000ull #define NIC3_TXE1_MAX_OFFSET 0x2040 #define NIC3_TXE1_SECTION 0x1000 #define mmNIC3_TXB_BASE 0x7FFCDB4000ull #define NIC3_TXB_MAX_OFFSET 0xD400 #define NIC3_TXB_SECTION 0x1000 #define mmNIC3_TMR_BASE 0x7FFCDB5000ull #define NIC3_TMR_MAX_OFFSET 0x1600 #define NIC3_TMR_SECTION 0x1000 #define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull #define NIC3_TX_GW_MAX_OFFSET 0x1400 #define NIC3_TX_GW_SECTION 0x2000 #define mmNIC3_TS_BASE 0x7FFCDB8000ull #define NIC3_TS_MAX_OFFSET 0xE640 #define NIC3_TS_SECTION 0x2000 #define mmNIC3_PM_BASE 0x7FFCDBA000ull #define NIC3_PM_MAX_OFFSET 0x1F00 #define NIC3_PM_SECTION 0x6000 #define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull #define NIC4_MAC_CH0_MAX_OFFSET 0x8400 #define NIC4_MAC_CH0_SECTION 0x1000 #define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull #define NIC4_MAC_CH1_MAX_OFFSET 0x8400 #define NIC4_MAC_CH1_SECTION 0x1000 #define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull #define NIC4_MAC_CH2_MAX_OFFSET 0x8400 #define NIC4_MAC_CH2_SECTION 0x1000 #define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull #define NIC4_MAC_CH3_MAX_OFFSET 0x8400 #define NIC4_MAC_CH3_SECTION 0x1000 #define mmNIC4_STAT_BASE 0x7FFCDC4000ull #define NIC4_STAT_MAX_OFFSET 0x4D00 #define NIC4_STAT_SECTION 0x1000 #define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull #define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380 #define NIC4_MAC_XPCS91_SECTION 0x3000 #define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull #define NIC4_MAC_CORE_MAX_OFFSET 0x5400 #define NIC4_MAC_CORE_SECTION 0x1000 #define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull #define NIC4_MAC_AUX_MAX_OFFSET 0x3000 #define NIC4_MAC_AUX_SECTION 0xF000 #define mmNIC4_PHY_BASE 0x7FFCDD8000ull #define NIC4_PHY_MAX_OFFSET 0x3400 #define NIC4_PHY_SECTION 0x8000 #define mmNIC4_QM0_BASE 0x7FFCDE0000ull #define NIC4_QM0_MAX_OFFSET 0xD040 #define NIC4_QM0_SECTION 0x2000 #define mmNIC4_QM1_BASE 0x7FFCDE2000ull #define NIC4_QM1_MAX_OFFSET 0xD040 #define NIC4_QM1_SECTION 0x2000 #define mmNIC4_QPC0_BASE 0x7FFCDE4000ull #define NIC4_QPC0_MAX_OFFSET 0x7140 #define NIC4_QPC0_SECTION 0x1000 #define mmNIC4_QPC1_BASE 0x7FFCDE5000ull #define NIC4_QPC1_MAX_OFFSET 0x7140 #define NIC4_QPC1_SECTION 0x3000 #define mmNIC4_RXB_BASE 0x7FFCDE8000ull #define NIC4_RXB_MAX_OFFSET 0x6040 #define NIC4_RXB_SECTION 0x1000 #define mmNIC4_RXE0_BASE 0x7FFCDE9000ull #define NIC4_RXE0_MAX_OFFSET 0x2FC0 #define NIC4_RXE0_SECTION 0x1000 #define mmNIC4_RXE1_BASE 0x7FFCDEA000ull #define NIC4_RXE1_MAX_OFFSET 0x2FC0 #define NIC4_RXE1_SECTION 0x1000 #define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull #define NIC4_RX_GW_MAX_OFFSET 0x4540 #define NIC4_RX_GW_SECTION 0x5000 #define mmNIC4_TXS0_BASE 0x7FFCDF0000ull #define NIC4_TXS0_MAX_OFFSET 0x19C0 #define NIC4_TXS0_SECTION 0x1000 #define mmNIC4_TXS1_BASE 0x7FFCDF1000ull #define NIC4_TXS1_MAX_OFFSET 0x19C0 #define NIC4_TXS1_SECTION 0x1000 #define mmNIC4_TXE0_BASE 0x7FFCDF2000ull #define NIC4_TXE0_MAX_OFFSET 0x2040 #define NIC4_TXE0_SECTION 0x1000 #define mmNIC4_TXE1_BASE 0x7FFCDF3000ull #define NIC4_TXE1_MAX_OFFSET 0x2040 #define NIC4_TXE1_SECTION 0x1000 #define mmNIC4_TXB_BASE 0x7FFCDF4000ull #define NIC4_TXB_MAX_OFFSET 0xD400 #define NIC4_TXB_SECTION 0x1000 #define mmNIC4_TMR_BASE 0x7FFCDF5000ull #define NIC4_TMR_MAX_OFFSET 0x1600 #define NIC4_TMR_SECTION 0x1000 #define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull #define NIC4_TX_GW_MAX_OFFSET 0x1400 #define NIC4_TX_GW_SECTION 0x10000 #define mmTPC0_CFG_BASE 0x7FFCE06000ull #define TPC0_CFG_MAX_OFFSET 0xE400 #define TPC0_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull #define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull #define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull #define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull #define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull #define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull #define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull #define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull #define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull #define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull #define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull #define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull #define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull #define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull #define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull #define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull #define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull #define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 #define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull #define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC0_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull #define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull #define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull #define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull #define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull #define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull #define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull #define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull #define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull #define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull #define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull #define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull #define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull #define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull #define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull #define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull #define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull #define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 #define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull #define QM_TPC0_CFG_MAX_OFFSET 0xB800 #define QM_TPC0_CFG_SECTION 0x2780 #define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull #define TPC0_E2E_CRED_MAX_OFFSET 0x1680 #define TPC0_E2E_CRED_SECTION 0x1000 #define mmTPC0_QM_BASE 0x7FFCE08000ull #define TPC0_QM_MAX_OFFSET 0xD040 #define TPC0_QM_SECTION 0x3E000 #define mmTPC1_CFG_BASE 0x7FFCE46000ull #define TPC1_CFG_MAX_OFFSET 0xE400 #define TPC1_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull #define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull #define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull #define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull #define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull #define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull #define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull #define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull #define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull #define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull #define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull #define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull #define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull #define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull #define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull #define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull #define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull #define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 #define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull #define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC1_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull #define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull #define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull #define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull #define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull #define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull #define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull #define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull #define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull #define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull #define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull #define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull #define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull #define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull #define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull #define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull #define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull #define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 #define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull #define QM_TPC1_CFG_MAX_OFFSET 0xB800 #define QM_TPC1_CFG_SECTION 0x2780 #define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull #define TPC1_E2E_CRED_MAX_OFFSET 0x1680 #define TPC1_E2E_CRED_SECTION 0x1000 #define mmTPC1_QM_BASE 0x7FFCE48000ull #define TPC1_QM_MAX_OFFSET 0xD040 #define TPC1_QM_SECTION 0x3E000 #define mmTPC2_CFG_BASE 0x7FFCE86000ull #define TPC2_CFG_MAX_OFFSET 0xE400 #define TPC2_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull #define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull #define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull #define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull #define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull #define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull #define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull #define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull #define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull #define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull #define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull #define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull #define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull #define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull #define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull #define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull #define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull #define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 #define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull #define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC2_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull #define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull #define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull #define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull #define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull #define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull #define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull #define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull #define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull #define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull #define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull #define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull #define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull #define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull #define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull #define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull #define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull #define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 #define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull #define QM_TPC2_CFG_MAX_OFFSET 0xB800 #define QM_TPC2_CFG_SECTION 0x2780 #define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull #define TPC2_E2E_CRED_MAX_OFFSET 0x1680 #define TPC2_E2E_CRED_SECTION 0x1000 #define mmTPC2_QM_BASE 0x7FFCE88000ull #define TPC2_QM_MAX_OFFSET 0xD040 #define TPC2_QM_SECTION 0x3E000 #define mmTPC3_CFG_BASE 0x7FFCEC6000ull #define TPC3_CFG_MAX_OFFSET 0xE400 #define TPC3_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull #define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull #define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull #define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull #define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull #define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull #define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull #define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull #define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull #define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull #define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull #define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull #define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull #define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull #define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull #define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull #define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull #define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 #define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull #define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC3_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull #define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull #define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull #define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull #define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull #define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull #define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull #define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull #define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull #define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull #define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull #define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull #define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull #define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull #define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull #define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull #define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull #define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 #define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull #define QM_TPC3_CFG_MAX_OFFSET 0xB800 #define QM_TPC3_CFG_SECTION 0x2780 #define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull #define TPC3_E2E_CRED_MAX_OFFSET 0x1680 #define TPC3_E2E_CRED_SECTION 0x1000 #define mmTPC3_QM_BASE 0x7FFCEC8000ull #define TPC3_QM_MAX_OFFSET 0xD040 #define TPC3_QM_SECTION 0x3E000 #define mmTPC4_CFG_BASE 0x7FFCF06000ull #define TPC4_CFG_MAX_OFFSET 0xE400 #define TPC4_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull #define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull #define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull #define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull #define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull #define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull #define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull #define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull #define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull #define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull #define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull #define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull #define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull #define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull #define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull #define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull #define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull #define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 #define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull #define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC4_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull #define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull #define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull #define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull #define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull #define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull #define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull #define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull #define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull #define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull #define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull #define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull #define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull #define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull #define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull #define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull #define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull #define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 #define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull #define QM_TPC4_CFG_MAX_OFFSET 0xB800 #define QM_TPC4_CFG_SECTION 0x2780 #define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull #define TPC4_E2E_CRED_MAX_OFFSET 0x1680 #define TPC4_E2E_CRED_SECTION 0x1000 #define mmTPC4_QM_BASE 0x7FFCF08000ull #define TPC4_QM_MAX_OFFSET 0xD040 #define TPC4_QM_SECTION 0x3E000 #define mmTPC5_CFG_BASE 0x7FFCF46000ull #define TPC5_CFG_MAX_OFFSET 0xE400 #define TPC5_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull #define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull #define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull #define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull #define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull #define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull #define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull #define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull #define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull #define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull #define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull #define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull #define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull #define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull #define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull #define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull #define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull #define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 #define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull #define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC5_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull #define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull #define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull #define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull #define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull #define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull #define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull #define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull #define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull #define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull #define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull #define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull #define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull #define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull #define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull #define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull #define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull #define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 #define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull #define QM_TPC5_CFG_MAX_OFFSET 0xB800 #define QM_TPC5_CFG_SECTION 0x2780 #define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull #define TPC5_E2E_CRED_MAX_OFFSET 0x1680 #define TPC5_E2E_CRED_SECTION 0x1000 #define mmTPC5_QM_BASE 0x7FFCF48000ull #define TPC5_QM_MAX_OFFSET 0xD040 #define TPC5_QM_SECTION 0x3E000 #define mmTPC6_CFG_BASE 0x7FFCF86000ull #define TPC6_CFG_MAX_OFFSET 0xE400 #define TPC6_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull #define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull #define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull #define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull #define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull #define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull #define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull #define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull #define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull #define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull #define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull #define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull #define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull #define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull #define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull #define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull #define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull #define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 #define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull #define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC6_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull #define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull #define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull #define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull #define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull #define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull #define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull #define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull #define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull #define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull #define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull #define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull #define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull #define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull #define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull #define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull #define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull #define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 #define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull #define QM_TPC6_CFG_MAX_OFFSET 0xB800 #define QM_TPC6_CFG_SECTION 0x2780 #define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull #define TPC6_E2E_CRED_MAX_OFFSET 0x1680 #define TPC6_E2E_CRED_SECTION 0x1000 #define mmTPC6_QM_BASE 0x7FFCF88000ull #define TPC6_QM_MAX_OFFSET 0xD040 #define TPC6_QM_SECTION 0x3E000 #define mmTPC7_CFG_BASE 0x7FFCFC6000ull #define TPC7_CFG_MAX_OFFSET 0xE400 #define TPC7_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull #define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull #define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull #define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull #define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull #define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull #define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull #define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull #define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull #define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull #define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull #define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull #define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull #define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull #define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull #define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull #define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull #define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 #define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull #define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC7_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull #define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull #define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull #define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull #define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull #define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull #define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull #define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull #define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull #define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull #define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull #define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull #define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull #define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull #define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull #define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull #define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull #define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 #define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull #define QM_TPC7_CFG_MAX_OFFSET 0xB800 #define QM_TPC7_CFG_SECTION 0x2780 #define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull #define TPC7_E2E_CRED_MAX_OFFSET 0x1680 #define TPC7_E2E_CRED_SECTION 0x1000 #define mmTPC7_QM_BASE 0x7FFCFC8000ull #define TPC7_QM_MAX_OFFSET 0xD040 #define TPC7_QM_SECTION 0x1038000 #define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull #define MME_S_ROM_TABLE_MAX_OFFSET 0x1000 #define MME_S_ROM_TABLE_SECTION 0x21000 #define mmMME0_ACC_STM_BASE 0x7FFE021000ull #define MME0_ACC_STM_MAX_OFFSET 0x1000 #define MME0_ACC_STM_SECTION 0x1000 #define mmMME0_ACC_CTI_BASE 0x7FFE022000ull #define MME0_ACC_CTI_MAX_OFFSET 0x1000 #define MME0_ACC_CTI_SECTION 0x1000 #define mmMME0_ACC_ETF_BASE 0x7FFE023000ull #define MME0_ACC_ETF_MAX_OFFSET 0x1000 #define MME0_ACC_ETF_SECTION 0x1000 #define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull #define MME0_ACC_SPMU_MAX_OFFSET 0x1000 #define MME0_ACC_SPMU_SECTION 0x1000 #define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull #define MME0_ACC_CTI0_MAX_OFFSET 0x1000 #define MME0_ACC_CTI0_SECTION 0x1000 #define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull #define MME0_ACC_CTI1_MAX_OFFSET 0x1000 #define MME0_ACC_CTI1_SECTION 0x1000 #define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull #define MME0_ACC_BMON0_MAX_OFFSET 0x1000 #define MME0_ACC_BMON0_SECTION 0x9000 #define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull #define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000 #define MME0_ACC_FUNNEL_SECTION 0x11000 #define mmMME0_SBAB_STM_BASE 0x7FFE041000ull #define MME0_SBAB_STM_MAX_OFFSET 0x1000 #define MME0_SBAB_STM_SECTION 0x1000 #define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull #define MME0_SBAB_CTI_MAX_OFFSET 0x1000 #define MME0_SBAB_CTI_SECTION 0x1000 #define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull #define MME0_SBAB_ETF_MAX_OFFSET 0x1000 #define MME0_SBAB_ETF_SECTION 0x1000 #define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull #define MME0_SBAB_SPMU_MAX_OFFSET 0x1000 #define MME0_SBAB_SPMU_SECTION 0x1000 #define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull #define MME0_SBAB_CTI0_MAX_OFFSET 0x1000 #define MME0_SBAB_CTI0_SECTION 0x1000 #define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull #define MME0_SBAB_CTI1_MAX_OFFSET 0x1000 #define MME0_SBAB_CTI1_SECTION 0x1000 #define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull #define MME0_SBAB_BMON0_MAX_OFFSET 0x1000 #define MME0_SBAB_BMON0_SECTION 0x1000 #define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull #define MME0_SBAB_BMON1_MAX_OFFSET 0x1000 #define MME0_SBAB_BMON1_SECTION 0x19000 #define mmMME0_CTRL_STM_BASE 0x7FFE061000ull #define MME0_CTRL_STM_MAX_OFFSET 0x1000 #define MME0_CTRL_STM_SECTION 0x1000 #define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull #define MME0_CTRL_CTI_MAX_OFFSET 0x1000 #define MME0_CTRL_CTI_SECTION 0x1000 #define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull #define MME0_CTRL_ETF_MAX_OFFSET 0x1000 #define MME0_CTRL_ETF_SECTION 0x1000 #define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull #define MME0_CTRL_SPMU_MAX_OFFSET 0x1000 #define MME0_CTRL_SPMU_SECTION 0x1000 #define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull #define MME0_CTRL_CTI0_MAX_OFFSET 0x1000 #define MME0_CTRL_CTI0_SECTION 0x1000 #define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull #define MME0_CTRL_CTI1_MAX_OFFSET 0x1000 #define MME0_CTRL_CTI1_SECTION 0x1000 #define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull #define MME0_CTRL_BMON0_MAX_OFFSET 0x1000 #define MME0_CTRL_BMON0_SECTION 0x1000 #define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull #define MME0_CTRL_BMON1_MAX_OFFSET 0x1000 #define MME0_CTRL_BMON1_SECTION 0x39000 #define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull #define MME1_ACC_STM_MAX_OFFSET 0x1000 #define MME1_ACC_STM_SECTION 0x1000 #define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull #define MME1_ACC_CTI_MAX_OFFSET 0x1000 #define MME1_ACC_CTI_SECTION 0x1000 #define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull #define MME1_ACC_ETF_MAX_OFFSET 0x1000 #define MME1_ACC_ETF_SECTION 0x1000 #define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull #define MME1_ACC_SPMU_MAX_OFFSET 0x1000 #define MME1_ACC_SPMU_SECTION 0x1000 #define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull #define MME1_ACC_CTI0_MAX_OFFSET 0x1000 #define MME1_ACC_CTI0_SECTION 0x1000 #define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull #define MME1_ACC_CTI1_MAX_OFFSET 0x1000 #define MME1_ACC_CTI1_SECTION 0x1000 #define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull #define MME1_ACC_BMON0_MAX_OFFSET 0x1000 #define MME1_ACC_BMON0_SECTION 0x9000 #define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull #define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000 #define MME1_ACC_FUNNEL_SECTION 0x11000 #define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull #define MME1_SBAB_STM_MAX_OFFSET 0x1000 #define MME1_SBAB_STM_SECTION 0x1000 #define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull #define MME1_SBAB_CTI_MAX_OFFSET 0x1000 #define MME1_SBAB_CTI_SECTION 0x1000 #define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull #define MME1_SBAB_ETF_MAX_OFFSET 0x1000 #define MME1_SBAB_ETF_SECTION 0x1000 #define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull #define MME1_SBAB_SPMU_MAX_OFFSET 0x1000 #define MME1_SBAB_SPMU_SECTION 0x1000 #define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull #define MME1_SBAB_CTI0_MAX_OFFSET 0x1000 #define MME1_SBAB_CTI0_SECTION 0x1000 #define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull #define MME1_SBAB_CTI1_MAX_OFFSET 0x1000 #define MME1_SBAB_CTI1_SECTION 0x1000 #define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull #define MME1_SBAB_BMON0_MAX_OFFSET 0x1000 #define MME1_SBAB_BMON0_SECTION 0x1000 #define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull #define MME1_SBAB_BMON1_MAX_OFFSET 0x1000 #define MME1_SBAB_BMON1_SECTION 0x19000 #define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull #define MME1_CTRL_STM_MAX_OFFSET 0x1000 #define MME1_CTRL_STM_SECTION 0x1000 #define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull #define MME1_CTRL_CTI_MAX_OFFSET 0x1000 #define MME1_CTRL_CTI_SECTION 0x1000 #define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull #define MME1_CTRL_ETF_MAX_OFFSET 0x1000 #define MME1_CTRL_ETF_SECTION 0x1000 #define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull #define MME1_CTRL_SPMU_MAX_OFFSET 0x1000 #define MME1_CTRL_SPMU_SECTION 0x1000 #define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull #define MME1_CTRL_CTI0_MAX_OFFSET 0x1000 #define MME1_CTRL_CTI0_SECTION 0x1000 #define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull #define MME1_CTRL_CTI1_MAX_OFFSET 0x1000 #define MME1_CTRL_CTI1_SECTION 0x1000 #define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull #define MME1_CTRL_BMON0_MAX_OFFSET 0x1000 #define MME1_CTRL_BMON0_SECTION 0x1000 #define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull #define MME1_CTRL_BMON1_MAX_OFFSET 0x1000 #define MME1_CTRL_BMON1_SECTION 0x18000 #define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull #define MME_N_ROM_TABLE_MAX_OFFSET 0x1000 #define MME_N_ROM_TABLE_SECTION 0x21000 #define mmMME2_ACC_STM_BASE 0x7FFE121000ull #define MME2_ACC_STM_MAX_OFFSET 0x1000 #define MME2_ACC_STM_SECTION 0x1000 #define mmMME2_ACC_CTI_BASE 0x7FFE122000ull #define MME2_ACC_CTI_MAX_OFFSET 0x1000 #define MME2_ACC_CTI_SECTION 0x1000 #define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull #define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000 #define MME2_MME2_ACC_ETF_SECTION 0x1000 #define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull #define MME2_ACC_SPMU_MAX_OFFSET 0x1000 #define MME2_ACC_SPMU_SECTION 0x1000 #define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull #define MME2_ACC_CTI0_MAX_OFFSET 0x1000 #define MME2_ACC_CTI0_SECTION 0x1000 #define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull #define MME2_ACC_CTI1_MAX_OFFSET 0x1000 #define MME2_ACC_CTI1_SECTION 0x1000 #define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull #define MME2_ACC_BMON0_MAX_OFFSET 0x1000 #define MME2_ACC_BMON0_SECTION 0x9000 #define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull #define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000 #define MME2_ACC_FUNNEL_SECTION 0x11000 #define mmMME2_SBAB_STM_BASE 0x7FFE141000ull #define MME2_SBAB_STM_MAX_OFFSET 0x1000 #define MME2_SBAB_STM_SECTION 0x1000 #define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull #define MME2_SBAB_CTI_MAX_OFFSET 0x1000 #define MME2_SBAB_CTI_SECTION 0x1000 #define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull #define MME2_SBAB_ETF_MAX_OFFSET 0x1000 #define MME2_SBAB_ETF_SECTION 0x1000 #define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull #define MME2_SBAB_SPMU_MAX_OFFSET 0x1000 #define MME2_SBAB_SPMU_SECTION 0x1000 #define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull #define MME2_SBAB_CTI0_MAX_OFFSET 0x1000 #define MME2_SBAB_CTI0_SECTION 0x1000 #define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull #define MME2_SBAB_CTI1_MAX_OFFSET 0x1000 #define MME2_SBAB_CTI1_SECTION 0x1000 #define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull #define MME2_SBAB_BMON0_MAX_OFFSET 0x1000 #define MME2_SBAB_BMON0_SECTION 0x1000 #define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull #define MME2_SBAB_BMON1_MAX_OFFSET 0x1000 #define MME2_SBAB_BMON1_SECTION 0x19000 #define mmMME2_CTRL_STM_BASE 0x7FFE161000ull #define MME2_CTRL_STM_MAX_OFFSET 0x1000 #define MME2_CTRL_STM_SECTION 0x1000 #define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull #define MME2_CTRL_CTI_MAX_OFFSET 0x1000 #define MME2_CTRL_CTI_SECTION 0x1000 #define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull #define MME2_CTRL_ETF_MAX_OFFSET 0x1000 #define MME2_CTRL_ETF_SECTION 0x1000 #define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull #define MME2_CTRL_SPMU_MAX_OFFSET 0x1000 #define MME2_CTRL_SPMU_SECTION 0x1000 #define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull #define MME2_CTRL_CTI0_MAX_OFFSET 0x1000 #define MME2_CTRL_CTI0_SECTION 0x1000 #define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull #define MME2_CTRL_CTI1_MAX_OFFSET 0x1000 #define MME2_CTRL_CTI1_SECTION 0x1000 #define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull #define MME2_CTRL_BMON0_MAX_OFFSET 0x1000 #define MME2_CTRL_BMON0_SECTION 0x1000 #define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull #define MME2_CTRL_BMON1_MAX_OFFSET 0x1000 #define MME2_CTRL_BMON1_SECTION 0x39000 #define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull #define MME3_ACC_STM_MAX_OFFSET 0x1000 #define MME3_ACC_STM_SECTION 0x1000 #define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull #define MME3_ACC_CTI_MAX_OFFSET 0x1000 #define MME3_ACC_CTI_SECTION 0x1000 #define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull #define MME3_ACC_ETF_MAX_OFFSET 0x1000 #define MME3_ACC_ETF_SECTION 0x1000 #define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull #define MME3_ACC_SPMU_MAX_OFFSET 0x1000 #define MME3_ACC_SPMU_SECTION 0x1000 #define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull #define MME3_ACC_CTI0_MAX_OFFSET 0x1000 #define MME3_ACC_CTI0_SECTION 0x1000 #define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull #define MME3_ACC_CTI1_MAX_OFFSET 0x1000 #define MME3_ACC_CTI1_SECTION 0x1000 #define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull #define MME3_ACC_BMON0_MAX_OFFSET 0x1000 #define MME3_ACC_BMON0_SECTION 0x9000 #define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull #define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000 #define MME3_ACC_FUNNEL_SECTION 0x11000 #define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull #define MME3_SBAB_STM_MAX_OFFSET 0x1000 #define MME3_SBAB_STM_SECTION 0x1000 #define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull #define MME3_SBAB_CTI_MAX_OFFSET 0x1000 #define MME3_SBAB_CTI_SECTION 0x1000 #define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull #define MME3_SBAB_ETF_MAX_OFFSET 0x1000 #define MME3_SBAB_ETF_SECTION 0x1000 #define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull #define MME3_SBAB_SPMU_MAX_OFFSET 0x1000 #define MME3_SBAB_SPMU_SECTION 0x1000 #define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull #define MME3_SBAB_CTI0_MAX_OFFSET 0x1000 #define MME3_SBAB_CTI0_SECTION 0x1000 #define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull #define MME3_SBAB_CTI1_MAX_OFFSET 0x1000 #define MME3_SBAB_CTI1_SECTION 0x1000 #define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull #define MME3_SBAB_BMON0_MAX_OFFSET 0x1000 #define MME3_SBAB_BMON0_SECTION 0x1000 #define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull #define MME3_SBAB_BMON1_MAX_OFFSET 0x1000 #define MME3_SBAB_BMON1_SECTION 0x19000 #define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull #define MME3_CTRL_STM_MAX_OFFSET 0x1000 #define MME3_CTRL_STM_SECTION 0x1000 #define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull #define MME3_CTRL_CTI_MAX_OFFSET 0x1000 #define MME3_CTRL_CTI_SECTION 0x1000 #define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull #define MME3_CTRL_ETF_MAX_OFFSET 0x1000 #define MME3_CTRL_ETF_SECTION 0x1000 #define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull #define MME3_CTRL_SPMU_MAX_OFFSET 0x1000 #define MME3_CTRL_SPMU_SECTION 0x1000 #define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull #define MME3_CTRL_CTI0_MAX_OFFSET 0x1000 #define MME3_CTRL_CTI0_SECTION 0x1000 #define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull #define MME3_CTRL_CTI1_MAX_OFFSET 0x1000 #define MME3_CTRL_CTI1_SECTION 0x1000 #define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull #define MME3_CTRL_BMON0_MAX_OFFSET 0x1000 #define MME3_CTRL_BMON0_SECTION 0x1000 #define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull #define MME3_CTRL_BMON1_MAX_OFFSET 0x1000 #define MME3_CTRL_BMON1_SECTION 0x18000 #define mmIC_ROM_TABLE_BASE 0x7FFE200000ull #define IC_ROM_TABLE_MAX_OFFSET 0x1000 #define IC_ROM_TABLE_SECTION 0x1000 #define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull #define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X0_FUNNEL_SECTION 0x8000 #define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull #define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X1_FUNNEL_SECTION 0x8000 #define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull #define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X2_FUNNEL_SECTION 0x8000 #define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull #define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X3_FUNNEL_SECTION 0x8000 #define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull #define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X4_FUNNEL_SECTION 0x8000 #define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull #define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X5_FUNNEL_SECTION 0x8000 #define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull #define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X6_FUNNEL_SECTION 0x8000 #define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull #define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y0_X7_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull #define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X0_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull #define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X1_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull #define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X2_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull #define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X3_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull #define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X4_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull #define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X5_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull #define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X6_FUNNEL_SECTION 0x8000 #define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull #define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y1_X7_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull #define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X0_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull #define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X1_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull #define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X2_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull #define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X3_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull #define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X4_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull #define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X5_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull #define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X6_FUNNEL_SECTION 0x8000 #define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull #define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y2_X7_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull #define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X0_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull #define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X1_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull #define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X2_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull #define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X4_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull #define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X3_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull #define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X5_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull #define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X6_FUNNEL_SECTION 0x8000 #define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull #define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000 #define SRAM_Y3_X7_FUNNEL_SECTION 0x7000 #define mmIF_ROM_TABLE_BASE 0x7FFE300000ull #define IF_ROM_TABLE_MAX_OFFSET 0x1000 #define IF_ROM_TABLE_SECTION 0x1000 #define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull #define SIF_FUNNEL_0_MAX_OFFSET 0x1000 #define SIF_FUNNEL_0_SECTION 0x10000 #define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull #define SIF_FUNNEL_1_MAX_OFFSET 0x1000 #define SIF_FUNNEL_1_SECTION 0x10000 #define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull #define SIF_FUNNEL_2_MAX_OFFSET 0x1000 #define SIF_FUNNEL_2_SECTION 0x10000 #define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull #define SIF_FUNNEL_3_MAX_OFFSET 0x1000 #define SIF_FUNNEL_3_SECTION 0x10000 #define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull #define SIF_FUNNEL_4_MAX_OFFSET 0x1000 #define SIF_FUNNEL_4_SECTION 0x10000 #define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull #define SIF_FUNNEL_5_MAX_OFFSET 0x1000 #define SIF_FUNNEL_5_SECTION 0x10000 #define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull #define SIF_FUNNEL_6_MAX_OFFSET 0x1000 #define SIF_FUNNEL_6_SECTION 0x10000 #define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull #define SIF_FUNNEL_7_MAX_OFFSET 0x1000 #define SIF_FUNNEL_7_SECTION 0x10000 #define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull #define NIF_FUNNEL_0_MAX_OFFSET 0x1000 #define NIF_FUNNEL_0_SECTION 0x10000 #define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull #define NIF_FUNNEL_1_MAX_OFFSET 0x1000 #define NIF_FUNNEL_1_SECTION 0x10000 #define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull #define NIF_FUNNEL_2_MAX_OFFSET 0x1000 #define NIF_FUNNEL_2_SECTION 0x10000 #define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull #define NIF_FUNNEL_3_MAX_OFFSET 0x1000 #define NIF_FUNNEL_3_SECTION 0x10000 #define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull #define NIF_FUNNEL_4_MAX_OFFSET 0x1000 #define NIF_FUNNEL_4_SECTION 0x10000 #define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull #define NIF_FUNNEL_5_MAX_OFFSET 0x1000 #define NIF_FUNNEL_5_SECTION 0x10000 #define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull #define NIF_FUNNEL_6_MAX_OFFSET 0x1000 #define NIF_FUNNEL_6_SECTION 0x10000 #define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull #define NIF_FUNNEL_7_MAX_OFFSET 0x1000 #define NIF_FUNNEL_7_SECTION 0xF000 #define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull #define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000 #define DMA_IF_ROM_TABLE_SECTION 0x1000 #define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull #define DMA_IF_W_S_STM_MAX_OFFSET 0x1000 #define DMA_IF_W_S_STM_SECTION 0x1000 #define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull #define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000 #define DMA_IF_W_S_CTI_SECTION 0x1000 #define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull #define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000 #define DMA_IF_W_S_ETF_SECTION 0x2000 #define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull #define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000 #define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000 #define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull #define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000 #define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000 #define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull #define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000 #define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull #define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000 #define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull #define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000 #define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull #define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000 #define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull #define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000 #define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull #define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000 #define DMA_IF_W_S_FUNNEL_SECTION 0x12000 #define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull #define DMA_IF_E_S_STM_MAX_OFFSET 0x1000 #define DMA_IF_E_S_STM_SECTION 0x1000 #define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull #define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000 #define DMA_IF_E_S_CTI_SECTION 0x1000 #define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull #define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000 #define DMA_IF_E_S_ETF_SECTION 0x2000 #define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull #define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000 #define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000 #define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull #define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000 #define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000 #define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull #define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000 #define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull #define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000 #define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull #define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000 #define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull #define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000 #define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull #define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000 #define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull #define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000 #define DMA_IF_E_S_FUNNEL_SECTION 0x12000 #define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull #define DMA_IF_W_N_STM_MAX_OFFSET 0x1000 #define DMA_IF_W_N_STM_SECTION 0x1000 #define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull #define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000 #define DMA_IF_W_N_CTI_SECTION 0x1000 #define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull #define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000 #define DMA_IF_W_N_ETF_SECTION 0x2000 #define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull #define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000 #define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000 #define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull #define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000 #define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000 #define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull #define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000 #define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull #define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000 #define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull #define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000 #define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull #define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000 #define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull #define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000 #define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull #define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000 #define DMA_IF_W_N_FUNNEL_SECTION 0x12000 #define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull #define DMA_IF_E_N_STM_MAX_OFFSET 0x1000 #define DMA_IF_E_N_STM_SECTION 0x1000 #define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull #define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000 #define DMA_IF_E_N_CTI_SECTION 0x1000 #define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull #define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000 #define DMA_IF_E_N_ETF_SECTION 0x2000 #define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull #define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000 #define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000 #define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull #define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000 #define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000 #define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull #define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000 #define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull #define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000 #define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull #define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000 #define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull #define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000 #define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull #define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000 #define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000 #define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull #define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000 #define DMA_IF_E_N_FUNNEL_SECTION 0x11000 #define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull #define CPU_ROM_TABLE_MAX_OFFSET 0x1000 #define CPU_ROM_TABLE_SECTION 0x1000 #define mmCPU_ETF_0_BASE 0x7FFE481000ull #define CPU_ETF_0_MAX_OFFSET 0x1000 #define CPU_ETF_0_SECTION 0x1000 #define mmCPU_ETF_1_BASE 0x7FFE482000ull #define CPU_ETF_1_MAX_OFFSET 0x1000 #define CPU_ETF_1_SECTION 0x2000 #define mmCPU_CTI_BASE 0x7FFE484000ull #define CPU_CTI_MAX_OFFSET 0x1000 #define CPU_CTI_SECTION 0x1000 #define mmCPU_FUNNEL_BASE 0x7FFE485000ull #define CPU_FUNNEL_MAX_OFFSET 0x1000 #define CPU_FUNNEL_SECTION 0x1000 #define mmCPU_STM_BASE 0x7FFE486000ull #define CPU_STM_MAX_OFFSET 0x1000 #define CPU_STM_SECTION 0x1000 #define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull #define CPU_CTI_TRACE_MAX_OFFSET 0x1000 #define CPU_CTI_TRACE_SECTION 0x1000 #define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull #define CPU_ETF_TRACE_MAX_OFFSET 0x1000 #define CPU_ETF_TRACE_SECTION 0x1000 #define mmCPU_WR_BMON_BASE 0x7FFE489000ull #define CPU_WR_BMON_MAX_OFFSET 0x1000 #define CPU_WR_BMON_SECTION 0x1000 #define mmCPU_RD_BMON_BASE 0x7FFE48A000ull #define CPU_RD_BMON_MAX_OFFSET 0x1000 #define CPU_RD_BMON_SECTION 0x76000 #define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull #define DMA_ROM_TABLE_MAX_OFFSET 0x1000 #define DMA_ROM_TABLE_SECTION 0x1000 #define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull #define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_0_CS_STM_SECTION 0x1000 #define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull #define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_0_CS_CTI_SECTION 0x1000 #define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull #define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_0_CS_ETF_SECTION 0x1000 #define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull #define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_0_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull #define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_0_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull #define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_0_USER_CTI_SECTION 0x1000 #define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull #define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_0_BMON_0_SECTION 0x1000 #define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull #define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_0_BMON_1_SECTION 0x19000 #define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull #define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_1_CS_STM_SECTION 0x1000 #define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull #define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_1_CS_CTI_SECTION 0x1000 #define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull #define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_1_CS_ETF_SECTION 0x1000 #define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull #define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_1_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull #define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_1_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull #define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_1_USER_CTI_SECTION 0x1000 #define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull #define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_1_BMON_0_SECTION 0x1000 #define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull #define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_1_BMON_1_SECTION 0x19000 #define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull #define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_2_CS_STM_SECTION 0x1000 #define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull #define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_2_CS_CTI_SECTION 0x1000 #define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull #define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_2_CS_ETF_SECTION 0x1000 #define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull #define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_2_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull #define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_2_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull #define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_2_USER_CTI_SECTION 0x1000 #define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull #define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_2_BMON_0_SECTION 0x1000 #define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull #define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_2_BMON_1_SECTION 0x19000 #define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull #define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_3_CS_STM_SECTION 0x1000 #define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull #define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_3_CS_CTI_SECTION 0x1000 #define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull #define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_3_CS_ETF_SECTION 0x1000 #define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull #define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_3_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull #define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_3_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull #define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_3_USER_CTI_SECTION 0x1000 #define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull #define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_3_BMON_0_SECTION 0x1000 #define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull #define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_3_BMON_1_SECTION 0x19000 #define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull #define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_4_CS_STM_SECTION 0x1000 #define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull #define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_4_CS_CTI_SECTION 0x1000 #define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull #define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_4_CS_ETF_SECTION 0x1000 #define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull #define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_4_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull #define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_4_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull #define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_4_USER_CTI_SECTION 0x1000 #define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull #define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_4_BMON_0_SECTION 0x1000 #define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull #define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_4_BMON_1_SECTION 0x19000 #define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull #define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_5_CS_STM_SECTION 0x1000 #define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull #define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_5_CS_CTI_SECTION 0x1000 #define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull #define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_5_CS_ETF_SECTION 0x1000 #define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull #define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_5_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull #define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_5_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull #define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_5_USER_CTI_SECTION 0x1000 #define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull #define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_5_BMON_0_SECTION 0x1000 #define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull #define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_5_BMON_1_SECTION 0x19000 #define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull #define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_6_CS_STM_SECTION 0x1000 #define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull #define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_6_CS_CTI_SECTION 0x1000 #define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull #define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_6_CS_ETF_SECTION 0x1000 #define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull #define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_6_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull #define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_6_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull #define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_6_USER_CTI_SECTION 0x1000 #define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull #define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_6_BMON_0_SECTION 0x1000 #define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull #define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_6_BMON_1_SECTION 0x19000 #define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull #define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000 #define DMA_CH_7_CS_STM_SECTION 0x1000 #define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull #define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000 #define DMA_CH_7_CS_CTI_SECTION 0x1000 #define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull #define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000 #define DMA_CH_7_CS_ETF_SECTION 0x1000 #define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull #define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000 #define DMA_CH_7_CS_SPMU_SECTION 0x1000 #define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull #define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000 #define DMA_CH_7_BMON_CTI_SECTION 0x1000 #define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull #define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000 #define DMA_CH_7_USER_CTI_SECTION 0x1000 #define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull #define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000 #define DMA_CH_7_BMON_0_SECTION 0x1000 #define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull #define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000 #define DMA_CH_7_BMON_1_SECTION 0x18000 #define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull #define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000 #define NIC_TPC_FUNNEL_W_S_SECTION 0x80000 #define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull #define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000 #define NIC_TPC_FUNNEL_E_S_SECTION 0x80000 #define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull #define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000 #define NIC_TPC_FUNNEL_W_N_SECTION 0x80000 #define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull #define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000 #define NIC_TPC_FUNNEL_E_N_SECTION 0x80000 #define mmCA53_BASE 0x7FFE800000ull #define CA53_MAX_OFFSET 0x141000 #define CA53_SECTION 0x400000 #define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull #define PCI_ROM_TABLE_MAX_OFFSET 0x1000 #define PCI_ROM_TABLE_SECTION 0x1000 #define mmPCIE_STM_BASE 0x7FFEC01000ull #define PCIE_STM_MAX_OFFSET 0x1000 #define PCIE_STM_SECTION 0x1000 #define mmPCIE_ETF_BASE 0x7FFEC02000ull #define PCIE_ETF_MAX_OFFSET 0x1000 #define PCIE_ETF_SECTION 0x1000 #define mmPCIE_CTI_0_BASE 0x7FFEC03000ull #define PCIE_CTI_0_MAX_OFFSET 0x1000 #define PCIE_CTI_0_SECTION 0x1000 #define mmPCIE_SPMU_BASE 0x7FFEC04000ull #define PCIE_SPMU_MAX_OFFSET 0x1000 #define PCIE_SPMU_SECTION 0x1000 #define mmPCIE_CTI_1_BASE 0x7FFEC05000ull #define PCIE_CTI_1_MAX_OFFSET 0x1000 #define PCIE_CTI_1_SECTION 0x1000 #define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull #define PCIE_FUNNEL_MAX_OFFSET 0x1000 #define PCIE_FUNNEL_SECTION 0x1000 #define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull #define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 #define PCIE_BMON_MSTR_WR_SECTION 0x1000 #define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull #define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 #define PCIE_BMON_MSTR_RD_SECTION 0x1000 #define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull #define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 #define PCIE_BMON_SLV_WR_SECTION 0x1000 #define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull #define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 #define PCIE_BMON_SLV_RD_SECTION 0x7000 #define mmMMU_CS_STM_BASE 0x7FFEC11000ull #define MMU_CS_STM_MAX_OFFSET 0x1000 #define MMU_CS_STM_SECTION 0x1000 #define mmMMU_CS_CTI_BASE 0x7FFEC12000ull #define MMU_CS_CTI_MAX_OFFSET 0x1000 #define MMU_CS_CTI_SECTION 0x1000 #define mmMMU_CS_ETF_BASE 0x7FFEC13000ull #define MMU_CS_ETF_MAX_OFFSET 0x1000 #define MMU_CS_ETF_SECTION 0x1000 #define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull #define MMU_CS_SPMU_MAX_OFFSET 0x1000 #define MMU_CS_SPMU_SECTION 0x1000 #define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull #define MMU_BMON_CTI_MAX_OFFSET 0x1000 #define MMU_BMON_CTI_SECTION 0x1000 #define mmMMU_USER_CTI_BASE 0x7FFEC16000ull #define MMU_USER_CTI_MAX_OFFSET 0x1000 #define MMU_USER_CTI_SECTION 0x1000 #define mmMMU_BMON_0_BASE 0x7FFEC17000ull #define MMU_BMON_0_MAX_OFFSET 0x1000 #define MMU_BMON_0_SECTION 0x1000 #define mmMMU_BMON_1_BASE 0x7FFEC18000ull #define MMU_BMON_1_MAX_OFFSET 0x1000 #define MMU_BMON_1_SECTION 0x28000 #define mmPSOC_CTI_BASE 0x7FFEC40000ull #define PSOC_CTI_MAX_OFFSET 0x1000 #define PSOC_CTI_SECTION 0x1000 #define mmPSOC_STM_BASE 0x7FFEC41000ull #define PSOC_STM_MAX_OFFSET 0x1000 #define PSOC_STM_SECTION 0x1000 #define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull #define PSOC_FUNNEL_MAX_OFFSET 0x1000 #define PSOC_FUNNEL_SECTION 0x1000 #define mmPSOC_ETR_BASE 0x7FFEC43000ull #define PSOC_ETR_MAX_OFFSET 0x1000 #define PSOC_ETR_SECTION 0x1000 #define mmPSOC_ETF_BASE 0x7FFEC44000ull #define PSOC_ETF_MAX_OFFSET 0x1000 #define PSOC_ETF_SECTION 0x1000 #define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull #define PSOC_TS_CTI_MAX_OFFSET 0x1000 #define PSOC_TS_CTI_SECTION 0xB000 #define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull #define TOP_ROM_TABLE_MAX_OFFSET 0x1000 #define TOP_ROM_TABLE_SECTION 0x70000 #define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull #define NIC0_ROM_TABLE_MAX_OFFSET 0x1000 #define NIC0_ROM_TABLE_SECTION 0x1000 #define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull #define STM_0_NIC0_DBG_MAX_OFFSET 0x21000 #define STM_0_NIC0_DBG_SECTION 0x1000 #define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull #define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 #define CTI_0_NIC0_DBG_SECTION 0x1000 #define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull #define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000 #define ETF_0_NIC0_DBG_SECTION 0x1000 #define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull #define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000 #define SPMU_0_NIC0_DBG_SECTION 0x2000 #define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull #define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 #define USER_CTI_0_NIC0_DBG_SECTION 0xB000 #define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull #define STM_1_NIC0_DBG_MAX_OFFSET 0x1000 #define STM_1_NIC0_DBG_SECTION 0x1000 #define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull #define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 #define CTI_1_NIC0_DBG_SECTION 0x1000 #define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull #define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000 #define ETF_1_NIC0_DBG_SECTION 0x1000 #define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull #define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000 #define SPMU_1_NIC0_DBG_SECTION 0x1000 #define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull #define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000 #define BMON_CTI_NIC0_DBG_SECTION 0x1000 #define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull #define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 #define USER_CTI_1_NIC0_DBG_SECTION 0x1000 #define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull #define BMON0_NIC0_DBG_MAX_OFFSET 0x1000 #define BMON0_NIC0_DBG_SECTION 0x1000 #define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull #define BMON1_NIC0_DBG_MAX_OFFSET 0x1000 #define BMON1_NIC0_DBG_SECTION 0x1000 #define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull #define BMON2_NIC0_DBG_MAX_OFFSET 0x1000 #define BMON2_NIC0_DBG_SECTION 0x1000 #define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull #define BMON3_NIC0_DBG_MAX_OFFSET 0x1000 #define BMON3_NIC0_DBG_SECTION 0x1000 #define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull #define BMON4_NIC0_DBG_MAX_OFFSET 0x1000 #define BMON4_NIC0_DBG_SECTION 0x6000 #define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull #define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000 #define FUNNEL_NIC0_DBG_SECTION 0x1F000 #define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull #define NIC1_ROM_TABLE_MAX_OFFSET 0x1000 #define NIC1_ROM_TABLE_SECTION 0x1000 #define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull #define STM_0_NIC1_DBG_MAX_OFFSET 0x21000 #define STM_0_NIC1_DBG_SECTION 0x1000 #define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull #define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 #define CTI_0_NIC1_DBG_SECTION 0x1000 #define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull #define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000 #define ETF_0_NIC1_DBG_SECTION 0x1000 #define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull #define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000 #define SPMU_0_NIC1_DBG_SECTION 0x2000 #define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull #define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 #define USER_CTI_0_NIC1_DBG_SECTION 0xB000 #define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull #define STM_1_NIC1_DBG_MAX_OFFSET 0x1000 #define STM_1_NIC1_DBG_SECTION 0x1000 #define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull #define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 #define CTI_1_NIC1_DBG_SECTION 0x1000 #define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull #define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000 #define ETF_1_NIC1_DBG_SECTION 0x1000 #define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull #define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000 #define SPMU_1_NIC1_DBG_SECTION 0x1000 #define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull #define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000 #define BMON_CTI_NIC1_DBG_SECTION 0x1000 #define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull #define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 #define USER_CTI_1_NIC1_DBG_SECTION 0x1000 #define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull #define BMON0_NIC1_DBG_MAX_OFFSET 0x1000 #define BMON0_NIC1_DBG_SECTION 0x1000 #define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull #define BMON1_NIC1_DBG_MAX_OFFSET 0x1000 #define BMON1_NIC1_DBG_SECTION 0x1000 #define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull #define BMON2_NIC1_DBG_MAX_OFFSET 0x1000 #define BMON2_NIC1_DBG_SECTION 0x1000 #define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull #define BMON3_NIC1_DBG_MAX_OFFSET 0x1000 #define BMON3_NIC1_DBG_SECTION 0x1000 #define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull #define BMON4_NIC1_DBG_MAX_OFFSET 0x1000 #define BMON4_NIC1_DBG_SECTION 0x6000 #define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull #define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000 #define FUNNEL_NIC1_DBG_SECTION 0x1F000 #define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull #define NIC2_ROM_TABLE_MAX_OFFSET 0x1000 #define NIC2_ROM_TABLE_SECTION 0x1000 #define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull #define STM_0_NIC2_DBG_MAX_OFFSET 0x21000 #define STM_0_NIC2_DBG_SECTION 0x1000 #define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull #define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 #define CTI_0_NIC2_DBG_SECTION 0x1000 #define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull #define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000 #define ETF_0_NIC2_DBG_SECTION 0x1000 #define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull #define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000 #define SPMU_0_NIC2_DBG_SECTION 0x2000 #define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull #define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 #define USER_CTI_0_NIC2_DBG_SECTION 0xB000 #define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull #define STM_1_NIC2_DBG_MAX_OFFSET 0x1000 #define STM_1_NIC2_DBG_SECTION 0x1000 #define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull #define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 #define CTI_1_NIC2_DBG_SECTION 0x1000 #define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull #define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000 #define ETF_1_NIC2_DBG_SECTION 0x1000 #define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull #define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000 #define SPMU_1_NIC2_DBG_SECTION 0x1000 #define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull #define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000 #define BMON_CTI_NIC2_DBG_SECTION 0x1000 #define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull #define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 #define USER_CTI_1_NIC2_DBG_SECTION 0x1000 #define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull #define BMON0_NIC2_DBG_MAX_OFFSET 0x1000 #define BMON0_NIC2_DBG_SECTION 0x1000 #define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull #define BMON1_NIC2_DBG_MAX_OFFSET 0x1000 #define BMON1_NIC2_DBG_SECTION 0x1000 #define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull #define BMON2_NIC2_DBG_MAX_OFFSET 0x1000 #define BMON2_NIC2_DBG_SECTION 0x1000 #define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull #define BMON3_NIC2_DBG_MAX_OFFSET 0x1000 #define BMON3_NIC2_DBG_SECTION 0x1000 #define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull #define BMON4_NIC2_DBG_MAX_OFFSET 0x1000 #define BMON4_NIC2_DBG_SECTION 0x6000 #define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull #define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000 #define FUNNEL_NIC2_DBG_SECTION 0x1F000 #define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull #define NIC3_ROM_TABLE_MAX_OFFSET 0x1000 #define NIC3_ROM_TABLE_SECTION 0x1000 #define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull #define STM_0_NIC3_DBG_MAX_OFFSET 0x21000 #define STM_0_NIC3_DBG_SECTION 0x1000 #define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull #define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 #define CTI_0_NIC3_DBG_SECTION 0x1000 #define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull #define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000 #define ETF_0_NIC3_DBG_SECTION 0x1000 #define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull #define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000 #define SPMU_0_NIC3_DBG_SECTION 0x2000 #define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull #define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 #define USER_CTI_0_NIC3_DBG_SECTION 0xB000 #define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull #define STM_1_NIC3_DBG_MAX_OFFSET 0x1000 #define STM_1_NIC3_DBG_SECTION 0x1000 #define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull #define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 #define CTI_1_NIC3_DBG_SECTION 0x1000 #define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull #define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000 #define ETF_1_NIC3_DBG_SECTION 0x1000 #define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull #define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000 #define SPMU_1_NIC3_DBG_SECTION 0x1000 #define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull #define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000 #define BMON_CTI_NIC3_DBG_SECTION 0x1000 #define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull #define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 #define USER_CTI_1_NIC3_DBG_SECTION 0x1000 #define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull #define BMON0_NIC3_DBG_MAX_OFFSET 0x1000 #define BMON0_NIC3_DBG_SECTION 0x1000 #define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull #define BMON1_NIC3_DBG_MAX_OFFSET 0x1000 #define BMON1_NIC3_DBG_SECTION 0x1000 #define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull #define BMON2_NIC3_DBG_MAX_OFFSET 0x1000 #define BMON2_NIC3_DBG_SECTION 0x1000 #define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull #define BMON3_NIC3_DBG_MAX_OFFSET 0x1000 #define BMON3_NIC3_DBG_SECTION 0x1000 #define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull #define BMON4_NIC3_DBG_MAX_OFFSET 0x1000 #define BMON4_NIC3_DBG_SECTION 0x6000 #define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull #define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000 #define FUNNEL_NIC3_DBG_SECTION 0x1F000 #define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull #define NIC4_ROM_TABLE_MAX_OFFSET 0x1000 #define NIC4_ROM_TABLE_SECTION 0x1000 #define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull #define STM_0_NIC4_DBG_MAX_OFFSET 0x21000 #define STM_0_NIC4_DBG_SECTION 0x1000 #define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull #define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 #define CTI_0_NIC4_DBG_SECTION 0x1000 #define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull #define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000 #define ETF_0_NIC4_DBG_SECTION 0x1000 #define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull #define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000 #define SPMU_0_NIC4_DBG_SECTION 0x2000 #define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull #define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 #define USER_CTI_0_NIC4_DBG_SECTION 0xB000 #define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull #define STM_1_NIC4_DBG_MAX_OFFSET 0x1000 #define STM_1_NIC4_DBG_SECTION 0x1000 #define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull #define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 #define CTI_1_NIC4_DBG_SECTION 0x1000 #define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull #define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000 #define ETF_1_NIC4_DBG_SECTION 0x1000 #define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull #define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000 #define SPMU_1_NIC4_DBG_SECTION 0x1000 #define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull #define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000 #define BMON_CTI_NIC4_DBG_SECTION 0x1000 #define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull #define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 #define USER_CTI_1_NIC4_DBG_SECTION 0x1000 #define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull #define BMON0_NIC4_DBG_MAX_OFFSET 0x1000 #define BMON0_NIC4_DBG_SECTION 0x1000 #define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull #define BMON1_NIC4_DBG_MAX_OFFSET 0x1000 #define BMON1_NIC4_DBG_SECTION 0x1000 #define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull #define BMON2_NIC4_DBG_MAX_OFFSET 0x1000 #define BMON2_NIC4_DBG_SECTION 0x1000 #define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull #define BMON3_NIC4_DBG_MAX_OFFSET 0x1000 #define BMON3_NIC4_DBG_SECTION 0x1000 #define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull #define BMON4_NIC4_DBG_MAX_OFFSET 0x1000 #define BMON4_NIC4_DBG_SECTION 0x6000 #define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull #define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000 #define FUNNEL_NIC4_DBG_SECTION 0x21F000 #define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull #define TPC0_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC0_ROM_TABLE_SECTION 0x1000 #define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull #define TPC0_EML_SPMU_MAX_OFFSET 0x1000 #define TPC0_EML_SPMU_SECTION 0x1000 #define mmTPC0_EML_ETF_BASE 0x7FFF002000ull #define TPC0_EML_ETF_MAX_OFFSET 0x1000 #define TPC0_EML_ETF_SECTION 0x1000 #define mmTPC0_EML_STM_BASE 0x7FFF003000ull #define TPC0_EML_STM_MAX_OFFSET 0x1000 #define TPC0_EML_STM_SECTION 0x2000 #define mmTPC0_EML_CTI_BASE 0x7FFF005000ull #define TPC0_EML_CTI_MAX_OFFSET 0x1000 #define TPC0_EML_CTI_SECTION 0x1000 #define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull #define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC0_EML_FUNNEL_SECTION 0x1000 #define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull #define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC0_EML_BUSMON_0_SECTION 0x1000 #define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull #define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC0_EML_BUSMON_1_SECTION 0x1000 #define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull #define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC0_EML_BUSMON_2_SECTION 0x1000 #define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull #define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC0_EML_BUSMON_3_SECTION 0x36000 #define mmTPC0_EML_CFG_BASE 0x7FFF040000ull #define TPC0_EML_CFG_MAX_OFFSET 0x3380 #define TPC0_EML_CFG_SECTION 0x1000 #define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull #define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC0_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull #define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull #define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull #define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull #define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull #define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull #define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull #define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull #define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull #define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull #define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull #define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull #define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull #define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull #define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull #define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull #define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull #define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull #define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull #define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull #define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull #define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull #define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull #define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull #define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull #define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull #define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull #define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull #define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull #define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull #define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull #define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull #define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull #define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull #define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull #define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull #define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC0_EML_TPC_CFG_SECTION 0x2780 #define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull #define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC0_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull #define TPC0_EML_CS_MAX_OFFSET 0x1000 #define TPC0_EML_CS_SECTION 0x1000 #define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull #define TPC1_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC1_ROM_TABLE_SECTION 0x1000 #define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull #define TPC1_EML_SPMU_MAX_OFFSET 0x1000 #define TPC1_EML_SPMU_SECTION 0x1000 #define mmTPC1_EML_ETF_BASE 0x7FFF202000ull #define TPC1_EML_ETF_MAX_OFFSET 0x1000 #define TPC1_EML_ETF_SECTION 0x1000 #define mmTPC1_EML_STM_BASE 0x7FFF203000ull #define TPC1_EML_STM_MAX_OFFSET 0x1000 #define TPC1_EML_STM_SECTION 0x2000 #define mmTPC1_EML_CTI_BASE 0x7FFF205000ull #define TPC1_EML_CTI_MAX_OFFSET 0x1000 #define TPC1_EML_CTI_SECTION 0x1000 #define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull #define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC1_EML_FUNNEL_SECTION 0x1000 #define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull #define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC1_EML_BUSMON_0_SECTION 0x1000 #define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull #define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC1_EML_BUSMON_1_SECTION 0x1000 #define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull #define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC1_EML_BUSMON_2_SECTION 0x1000 #define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull #define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC1_EML_BUSMON_3_SECTION 0x36000 #define mmTPC1_EML_CFG_BASE 0x7FFF240000ull #define TPC1_EML_CFG_MAX_OFFSET 0x3380 #define TPC1_EML_CFG_SECTION 0x1000 #define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull #define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC1_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull #define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull #define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull #define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull #define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull #define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull #define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull #define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull #define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull #define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull #define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull #define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull #define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull #define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull #define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull #define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull #define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull #define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull #define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull #define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull #define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull #define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull #define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull #define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull #define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull #define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull #define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull #define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull #define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull #define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull #define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull #define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull #define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull #define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull #define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull #define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull #define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC1_EML_TPC_CFG_SECTION 0x2780 #define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull #define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC1_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull #define TPC1_EML_CS_MAX_OFFSET 0x1000 #define TPC1_EML_CS_SECTION 0x1000 #define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull #define TPC2_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC2_ROM_TABLE_SECTION 0x1000 #define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull #define TPC2_EML_SPMU_MAX_OFFSET 0x1000 #define TPC2_EML_SPMU_SECTION 0x1000 #define mmTPC2_EML_ETF_BASE 0x7FFF402000ull #define TPC2_EML_ETF_MAX_OFFSET 0x1000 #define TPC2_EML_ETF_SECTION 0x1000 #define mmTPC2_EML_STM_BASE 0x7FFF403000ull #define TPC2_EML_STM_MAX_OFFSET 0x1000 #define TPC2_EML_STM_SECTION 0x2000 #define mmTPC2_EML_CTI_BASE 0x7FFF405000ull #define TPC2_EML_CTI_MAX_OFFSET 0x1000 #define TPC2_EML_CTI_SECTION 0x1000 #define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull #define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC2_EML_FUNNEL_SECTION 0x1000 #define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull #define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC2_EML_BUSMON_0_SECTION 0x1000 #define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull #define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC2_EML_BUSMON_1_SECTION 0x1000 #define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull #define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC2_EML_BUSMON_2_SECTION 0x1000 #define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull #define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC2_EML_BUSMON_3_SECTION 0x36000 #define mmTPC2_EML_CFG_BASE 0x7FFF440000ull #define TPC2_EML_CFG_MAX_OFFSET 0x3380 #define TPC2_EML_CFG_SECTION 0x1000 #define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull #define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC2_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull #define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull #define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull #define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull #define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull #define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull #define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull #define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull #define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull #define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull #define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull #define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull #define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull #define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull #define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull #define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull #define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull #define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull #define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull #define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull #define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull #define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull #define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull #define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull #define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull #define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull #define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull #define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull #define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull #define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull #define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull #define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull #define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull #define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull #define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull #define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull #define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC2_EML_TPC_CFG_SECTION 0x2780 #define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull #define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC2_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull #define TPC2_EML_CS_MAX_OFFSET 0x1000 #define TPC2_EML_CS_SECTION 0x1000 #define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull #define TPC3_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC3_ROM_TABLE_SECTION 0x1000 #define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull #define TPC3_EML_SPMU_MAX_OFFSET 0x1000 #define TPC3_EML_SPMU_SECTION 0x1000 #define mmTPC3_EML_ETF_BASE 0x7FFF602000ull #define TPC3_EML_ETF_MAX_OFFSET 0x1000 #define TPC3_EML_ETF_SECTION 0x1000 #define mmTPC3_EML_STM_BASE 0x7FFF603000ull #define TPC3_EML_STM_MAX_OFFSET 0x1000 #define TPC3_EML_STM_SECTION 0x2000 #define mmTPC3_EML_CTI_BASE 0x7FFF605000ull #define TPC3_EML_CTI_MAX_OFFSET 0x1000 #define TPC3_EML_CTI_SECTION 0x1000 #define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull #define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC3_EML_FUNNEL_SECTION 0x1000 #define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull #define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC3_EML_BUSMON_0_SECTION 0x1000 #define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull #define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC3_EML_BUSMON_1_SECTION 0x1000 #define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull #define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC3_EML_BUSMON_2_SECTION 0x1000 #define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull #define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC3_EML_BUSMON_3_SECTION 0x36000 #define mmTPC3_EML_CFG_BASE 0x7FFF640000ull #define TPC3_EML_CFG_MAX_OFFSET 0x3380 #define TPC3_EML_CFG_SECTION 0x1000 #define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull #define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC3_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull #define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull #define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull #define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull #define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull #define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull #define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull #define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull #define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull #define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull #define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull #define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull #define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull #define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull #define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull #define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull #define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull #define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull #define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull #define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull #define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull #define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull #define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull #define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull #define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull #define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull #define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull #define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull #define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull #define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull #define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull #define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull #define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull #define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull #define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull #define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull #define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC3_EML_TPC_CFG_SECTION 0x2780 #define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull #define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC3_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull #define TPC3_EML_CS_MAX_OFFSET 0x1000 #define TPC3_EML_CS_SECTION 0x1000 #define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull #define TPC4_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC4_ROM_TABLE_SECTION 0x1000 #define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull #define TPC4_EML_SPMU_MAX_OFFSET 0x1000 #define TPC4_EML_SPMU_SECTION 0x1000 #define mmTPC4_EML_ETF_BASE 0x7FFF802000ull #define TPC4_EML_ETF_MAX_OFFSET 0x1000 #define TPC4_EML_ETF_SECTION 0x1000 #define mmTPC4_EML_STM_BASE 0x7FFF803000ull #define TPC4_EML_STM_MAX_OFFSET 0x1000 #define TPC4_EML_STM_SECTION 0x2000 #define mmTPC4_EML_CTI_BASE 0x7FFF805000ull #define TPC4_EML_CTI_MAX_OFFSET 0x1000 #define TPC4_EML_CTI_SECTION 0x1000 #define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull #define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC4_EML_FUNNEL_SECTION 0x1000 #define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull #define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC4_EML_BUSMON_0_SECTION 0x1000 #define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull #define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC4_EML_BUSMON_1_SECTION 0x1000 #define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull #define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC4_EML_BUSMON_2_SECTION 0x1000 #define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull #define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC4_EML_BUSMON_3_SECTION 0x36000 #define mmTPC4_EML_CFG_BASE 0x7FFF840000ull #define TPC4_EML_CFG_MAX_OFFSET 0x3380 #define TPC4_EML_CFG_SECTION 0x1000 #define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull #define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC4_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull #define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull #define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull #define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull #define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull #define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull #define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull #define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull #define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull #define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull #define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull #define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull #define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull #define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull #define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull #define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull #define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull #define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull #define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull #define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull #define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull #define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull #define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull #define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull #define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull #define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull #define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull #define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull #define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull #define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull #define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull #define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull #define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull #define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull #define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull #define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull #define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC4_EML_TPC_CFG_SECTION 0x2780 #define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull #define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC4_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull #define TPC4_EML_CS_MAX_OFFSET 0x1000 #define TPC4_EML_CS_SECTION 0x1000 #define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull #define TPC5_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC5_ROM_TABLE_SECTION 0x1000 #define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull #define TPC5_EML_SPMU_MAX_OFFSET 0x1000 #define TPC5_EML_SPMU_SECTION 0x1000 #define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull #define TPC5_EML_ETF_MAX_OFFSET 0x1000 #define TPC5_EML_ETF_SECTION 0x1000 #define mmTPC5_EML_STM_BASE 0x7FFFA03000ull #define TPC5_EML_STM_MAX_OFFSET 0x1000 #define TPC5_EML_STM_SECTION 0x2000 #define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull #define TPC5_EML_CTI_MAX_OFFSET 0x1000 #define TPC5_EML_CTI_SECTION 0x1000 #define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull #define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC5_EML_FUNNEL_SECTION 0x1000 #define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull #define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC5_EML_BUSMON_0_SECTION 0x1000 #define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull #define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC5_EML_BUSMON_1_SECTION 0x1000 #define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull #define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC5_EML_BUSMON_2_SECTION 0x1000 #define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull #define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC5_EML_BUSMON_3_SECTION 0x36000 #define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull #define TPC5_EML_CFG_MAX_OFFSET 0x3380 #define TPC5_EML_CFG_SECTION 0x1000 #define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull #define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC5_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull #define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull #define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull #define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull #define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull #define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull #define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull #define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull #define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull #define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull #define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull #define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull #define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull #define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull #define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull #define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull #define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull #define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull #define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull #define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull #define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull #define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull #define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull #define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull #define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull #define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull #define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull #define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull #define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull #define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull #define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull #define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull #define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull #define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull #define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull #define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull #define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC5_EML_TPC_CFG_SECTION 0x2780 #define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull #define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC5_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull #define TPC5_EML_CS_MAX_OFFSET 0x1000 #define TPC5_EML_CS_SECTION 0x1000 #define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull #define TPC6_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC6_ROM_TABLE_SECTION 0x1000 #define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull #define TPC6_EML_SPMU_MAX_OFFSET 0x1000 #define TPC6_EML_SPMU_SECTION 0x1000 #define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull #define TPC6_EML_ETF_MAX_OFFSET 0x1000 #define TPC6_EML_ETF_SECTION 0x1000 #define mmTPC6_EML_STM_BASE 0x7FFFC03000ull #define TPC6_EML_STM_MAX_OFFSET 0x1000 #define TPC6_EML_STM_SECTION 0x2000 #define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull #define TPC6_EML_CTI_MAX_OFFSET 0x1000 #define TPC6_EML_CTI_SECTION 0x1000 #define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull #define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC6_EML_FUNNEL_SECTION 0x1000 #define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull #define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC6_EML_BUSMON_0_SECTION 0x1000 #define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull #define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC6_EML_BUSMON_1_SECTION 0x1000 #define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull #define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC6_EML_BUSMON_2_SECTION 0x1000 #define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull #define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC6_EML_BUSMON_3_SECTION 0x36000 #define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull #define TPC6_EML_CFG_MAX_OFFSET 0x3380 #define TPC6_EML_CFG_SECTION 0x1000 #define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull #define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC6_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull #define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull #define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull #define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull #define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull #define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull #define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull #define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull #define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull #define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull #define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull #define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull #define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull #define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull #define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull #define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull #define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull #define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull #define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull #define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull #define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull #define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull #define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull #define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull #define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull #define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull #define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull #define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull #define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull #define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull #define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull #define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull #define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull #define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull #define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull #define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull #define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC6_EML_TPC_CFG_SECTION 0x2780 #define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull #define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC6_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull #define TPC6_EML_CS_MAX_OFFSET 0x1000 #define TPC6_EML_CS_SECTION 0x1000 #define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull #define TPC7_ROM_TABLE_MAX_OFFSET 0x1000 #define TPC7_ROM_TABLE_SECTION 0x1000 #define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull #define TPC7_EML_SPMU_MAX_OFFSET 0x1000 #define TPC7_EML_SPMU_SECTION 0x1000 #define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull #define TPC7_EML_ETF_MAX_OFFSET 0x1000 #define TPC7_EML_ETF_SECTION 0x1000 #define mmTPC7_EML_STM_BASE 0x7FFFE03000ull #define TPC7_EML_STM_MAX_OFFSET 0x1000 #define TPC7_EML_STM_SECTION 0x2000 #define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull #define TPC7_EML_CTI_MAX_OFFSET 0x1000 #define TPC7_EML_CTI_SECTION 0x1000 #define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull #define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 #define TPC7_EML_FUNNEL_SECTION 0x1000 #define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull #define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 #define TPC7_EML_BUSMON_0_SECTION 0x1000 #define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull #define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 #define TPC7_EML_BUSMON_1_SECTION 0x1000 #define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull #define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 #define TPC7_EML_BUSMON_2_SECTION 0x1000 #define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull #define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 #define TPC7_EML_BUSMON_3_SECTION 0x36000 #define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull #define TPC7_EML_CFG_MAX_OFFSET 0x3380 #define TPC7_EML_CFG_SECTION 0x1000 #define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull #define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400 #define TPC7_EML_TPC_CFG_SECTION 0x4000 #define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull #define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull #define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull #define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull #define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull #define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull #define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull #define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull #define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull #define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull #define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull #define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull #define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull #define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull #define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull #define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull #define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull #define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 #define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 #define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull #define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 #define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780 #define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull #define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull #define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull #define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull #define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull #define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull #define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull #define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull #define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull #define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull #define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull #define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull #define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull #define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull #define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull #define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull #define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 #define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 #define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull #define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 #define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 #define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull #define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 #define QM_TPC7_EML_TPC_CFG_SECTION 0x2780 #define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull #define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040 #define TPC7_EML_TPC_QM_SECTION 0x1BD000 #define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull #define TPC7_EML_CS_MAX_OFFSET 0x1000 #endif /* GAUDI_BLOCKS_H_ */
