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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 | /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Loongson Technology Corporation Limited */ #include <asm/asm.h> #include <asm/export.h> #include <asm/loongarch.h> #include <asm/page.h> #include <asm/pgtable.h> #include <asm/regdef.h> #include <asm/stackframe.h> .macro tlb_do_page_fault, write SYM_FUNC_START(tlb_do_page_fault_\write) SAVE_ALL csrrd a2, LOONGARCH_CSR_BADV move a0, sp REG_S a2, sp, PT_BVADDR li.w a1, \write la.abs t0, do_page_fault jirl ra, t0, 0 RESTORE_ALL_AND_RET SYM_FUNC_END(tlb_do_page_fault_\write) .endm tlb_do_page_fault 0 tlb_do_page_fault 1 SYM_FUNC_START(handle_tlb_protect) BACKUP_T0T1 SAVE_ALL move a0, sp move a1, zero csrrd a2, LOONGARCH_CSR_BADV REG_S a2, sp, PT_BVADDR la.abs t0, do_page_fault jirl ra, t0, 0 RESTORE_ALL_AND_RET SYM_FUNC_END(handle_tlb_protect) SYM_FUNC_START(handle_tlb_load) csrwr t0, EXCEPTION_KS0 csrwr t1, EXCEPTION_KS1 csrwr ra, EXCEPTION_KS2 /* * The vmalloc handling is not in the hotpath. */ csrrd t0, LOONGARCH_CSR_BADV bltz t0, vmalloc_load csrrd t1, LOONGARCH_CSR_PGDL vmalloc_done_load: /* Get PGD offset in bytes */ srli.d t0, t0, PGDIR_SHIFT andi t0, t0, (PTRS_PER_PGD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #if CONFIG_PGTABLE_LEVELS > 3 csrrd t0, LOONGARCH_CSR_BADV ld.d t1, t1, 0 srli.d t0, t0, PUD_SHIFT andi t0, t0, (PTRS_PER_PUD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #endif #if CONFIG_PGTABLE_LEVELS > 2 csrrd t0, LOONGARCH_CSR_BADV ld.d t1, t1, 0 srli.d t0, t0, PMD_SHIFT andi t0, t0, (PTRS_PER_PMD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #endif ld.d ra, t1, 0 /* * For huge tlb entries, pmde doesn't contain an address but * instead contains the tlb pte. Check the PAGE_HUGE bit and * see if we need to jump to huge tlb processing. */ andi t0, ra, _PAGE_HUGE bnez t0, tlb_huge_update_load csrrd t0, LOONGARCH_CSR_BADV srli.d t0, t0, PAGE_SHIFT andi t0, t0, (PTRS_PER_PTE - 1) slli.d t0, t0, _PTE_T_LOG2 add.d t1, ra, t0 #ifdef CONFIG_SMP smp_pgtable_change_load: #endif #ifdef CONFIG_SMP ll.d t0, t1, 0 #else ld.d t0, t1, 0 #endif tlbsrch srli.d ra, t0, _PAGE_PRESENT_SHIFT andi ra, ra, 1 beqz ra, nopage_tlb_load ori t0, t0, _PAGE_VALID #ifdef CONFIG_SMP sc.d t0, t1, 0 beqz t0, smp_pgtable_change_load #else st.d t0, t1, 0 #endif ori t1, t1, 8 xori t1, t1, 8 ld.d t0, t1, 0 ld.d t1, t1, 8 csrwr t0, LOONGARCH_CSR_TLBELO0 csrwr t1, LOONGARCH_CSR_TLBELO1 tlbwr leave_load: csrrd t0, EXCEPTION_KS0 csrrd t1, EXCEPTION_KS1 csrrd ra, EXCEPTION_KS2 ertn #ifdef CONFIG_64BIT vmalloc_load: la.abs t1, swapper_pg_dir b vmalloc_done_load #endif /* * This is the entry point when build_tlbchange_handler_head * spots a huge page. */ tlb_huge_update_load: #ifdef CONFIG_SMP ll.d t0, t1, 0 #else ld.d t0, t1, 0 #endif srli.d ra, t0, _PAGE_PRESENT_SHIFT andi ra, ra, 1 beqz ra, nopage_tlb_load tlbsrch ori t0, t0, _PAGE_VALID #ifdef CONFIG_SMP sc.d t0, t1, 0 beqz t0, tlb_huge_update_load ld.d t0, t1, 0 #else st.d t0, t1, 0 #endif addu16i.d t1, zero, -(CSR_TLBIDX_EHINV >> 16) addi.d ra, t1, 0 csrxchg ra, t1, LOONGARCH_CSR_TLBIDX tlbwr csrxchg zero, t1, LOONGARCH_CSR_TLBIDX /* * A huge PTE describes an area the size of the * configured huge page size. This is twice the * of the large TLB entry size we intend to use. * A TLB entry half the size of the configured * huge page size is configured into entrylo0 * and entrylo1 to cover the contiguous huge PTE * address space. */ /* Huge page: Move Global bit */ xori t0, t0, _PAGE_HUGE lu12i.w t1, _PAGE_HGLOBAL >> 12 and t1, t0, t1 srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) or t0, t0, t1 addi.d ra, t0, 0 csrwr t0, LOONGARCH_CSR_TLBELO0 addi.d t0, ra, 0 /* Convert to entrylo1 */ addi.d t1, zero, 1 slli.d t1, t1, (HPAGE_SHIFT - 1) add.d t0, t0, t1 csrwr t0, LOONGARCH_CSR_TLBELO1 /* Set huge page tlb entry size */ addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) csrxchg t1, t0, LOONGARCH_CSR_TLBIDX tlbfill addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) csrxchg t1, t0, LOONGARCH_CSR_TLBIDX nopage_tlb_load: dbar 0 csrrd ra, EXCEPTION_KS2 la.abs t0, tlb_do_page_fault_0 jr t0 SYM_FUNC_END(handle_tlb_load) SYM_FUNC_START(handle_tlb_store) csrwr t0, EXCEPTION_KS0 csrwr t1, EXCEPTION_KS1 csrwr ra, EXCEPTION_KS2 /* * The vmalloc handling is not in the hotpath. */ csrrd t0, LOONGARCH_CSR_BADV bltz t0, vmalloc_store csrrd t1, LOONGARCH_CSR_PGDL vmalloc_done_store: /* Get PGD offset in bytes */ srli.d t0, t0, PGDIR_SHIFT andi t0, t0, (PTRS_PER_PGD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #if CONFIG_PGTABLE_LEVELS > 3 csrrd t0, LOONGARCH_CSR_BADV ld.d t1, t1, 0 srli.d t0, t0, PUD_SHIFT andi t0, t0, (PTRS_PER_PUD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #endif #if CONFIG_PGTABLE_LEVELS > 2 csrrd t0, LOONGARCH_CSR_BADV ld.d t1, t1, 0 srli.d t0, t0, PMD_SHIFT andi t0, t0, (PTRS_PER_PMD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #endif ld.d ra, t1, 0 /* * For huge tlb entries, pmde doesn't contain an address but * instead contains the tlb pte. Check the PAGE_HUGE bit and * see if we need to jump to huge tlb processing. */ andi t0, ra, _PAGE_HUGE bnez t0, tlb_huge_update_store csrrd t0, LOONGARCH_CSR_BADV srli.d t0, t0, PAGE_SHIFT andi t0, t0, (PTRS_PER_PTE - 1) slli.d t0, t0, _PTE_T_LOG2 add.d t1, ra, t0 #ifdef CONFIG_SMP smp_pgtable_change_store: #endif #ifdef CONFIG_SMP ll.d t0, t1, 0 #else ld.d t0, t1, 0 #endif tlbsrch srli.d ra, t0, _PAGE_PRESENT_SHIFT andi ra, ra, ((_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT) xori ra, ra, ((_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT) bnez ra, nopage_tlb_store ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) #ifdef CONFIG_SMP sc.d t0, t1, 0 beqz t0, smp_pgtable_change_store #else st.d t0, t1, 0 #endif ori t1, t1, 8 xori t1, t1, 8 ld.d t0, t1, 0 ld.d t1, t1, 8 csrwr t0, LOONGARCH_CSR_TLBELO0 csrwr t1, LOONGARCH_CSR_TLBELO1 tlbwr leave_store: csrrd t0, EXCEPTION_KS0 csrrd t1, EXCEPTION_KS1 csrrd ra, EXCEPTION_KS2 ertn #ifdef CONFIG_64BIT vmalloc_store: la.abs t1, swapper_pg_dir b vmalloc_done_store #endif /* * This is the entry point when build_tlbchange_handler_head * spots a huge page. */ tlb_huge_update_store: #ifdef CONFIG_SMP ll.d t0, t1, 0 #else ld.d t0, t1, 0 #endif srli.d ra, t0, _PAGE_PRESENT_SHIFT andi ra, ra, ((_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT) xori ra, ra, ((_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT) bnez ra, nopage_tlb_store tlbsrch ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) #ifdef CONFIG_SMP sc.d t0, t1, 0 beqz t0, tlb_huge_update_store ld.d t0, t1, 0 #else st.d t0, t1, 0 #endif addu16i.d t1, zero, -(CSR_TLBIDX_EHINV >> 16) addi.d ra, t1, 0 csrxchg ra, t1, LOONGARCH_CSR_TLBIDX tlbwr csrxchg zero, t1, LOONGARCH_CSR_TLBIDX /* * A huge PTE describes an area the size of the * configured huge page size. This is twice the * of the large TLB entry size we intend to use. * A TLB entry half the size of the configured * huge page size is configured into entrylo0 * and entrylo1 to cover the contiguous huge PTE * address space. */ /* Huge page: Move Global bit */ xori t0, t0, _PAGE_HUGE lu12i.w t1, _PAGE_HGLOBAL >> 12 and t1, t0, t1 srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) or t0, t0, t1 addi.d ra, t0, 0 csrwr t0, LOONGARCH_CSR_TLBELO0 addi.d t0, ra, 0 /* Convert to entrylo1 */ addi.d t1, zero, 1 slli.d t1, t1, (HPAGE_SHIFT - 1) add.d t0, t0, t1 csrwr t0, LOONGARCH_CSR_TLBELO1 /* Set huge page tlb entry size */ addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) csrxchg t1, t0, LOONGARCH_CSR_TLBIDX tlbfill /* Reset default page size */ addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) csrxchg t1, t0, LOONGARCH_CSR_TLBIDX nopage_tlb_store: dbar 0 csrrd ra, EXCEPTION_KS2 la.abs t0, tlb_do_page_fault_1 jr t0 SYM_FUNC_END(handle_tlb_store) SYM_FUNC_START(handle_tlb_modify) csrwr t0, EXCEPTION_KS0 csrwr t1, EXCEPTION_KS1 csrwr ra, EXCEPTION_KS2 /* * The vmalloc handling is not in the hotpath. */ csrrd t0, LOONGARCH_CSR_BADV bltz t0, vmalloc_modify csrrd t1, LOONGARCH_CSR_PGDL vmalloc_done_modify: /* Get PGD offset in bytes */ srli.d t0, t0, PGDIR_SHIFT andi t0, t0, (PTRS_PER_PGD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #if CONFIG_PGTABLE_LEVELS > 3 csrrd t0, LOONGARCH_CSR_BADV ld.d t1, t1, 0 srli.d t0, t0, PUD_SHIFT andi t0, t0, (PTRS_PER_PUD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #endif #if CONFIG_PGTABLE_LEVELS > 2 csrrd t0, LOONGARCH_CSR_BADV ld.d t1, t1, 0 srli.d t0, t0, PMD_SHIFT andi t0, t0, (PTRS_PER_PMD - 1) slli.d t0, t0, 3 add.d t1, t1, t0 #endif ld.d ra, t1, 0 /* * For huge tlb entries, pmde doesn't contain an address but * instead contains the tlb pte. Check the PAGE_HUGE bit and * see if we need to jump to huge tlb processing. */ andi t0, ra, _PAGE_HUGE bnez t0, tlb_huge_update_modify csrrd t0, LOONGARCH_CSR_BADV srli.d t0, t0, PAGE_SHIFT andi t0, t0, (PTRS_PER_PTE - 1) slli.d t0, t0, _PTE_T_LOG2 add.d t1, ra, t0 #ifdef CONFIG_SMP smp_pgtable_change_modify: #endif #ifdef CONFIG_SMP ll.d t0, t1, 0 #else ld.d t0, t1, 0 #endif tlbsrch srli.d ra, t0, _PAGE_WRITE_SHIFT andi ra, ra, 1 beqz ra, nopage_tlb_modify ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) #ifdef CONFIG_SMP sc.d t0, t1, 0 beqz t0, smp_pgtable_change_modify #else st.d t0, t1, 0 #endif ori t1, t1, 8 xori t1, t1, 8 ld.d t0, t1, 0 ld.d t1, t1, 8 csrwr t0, LOONGARCH_CSR_TLBELO0 csrwr t1, LOONGARCH_CSR_TLBELO1 tlbwr leave_modify: csrrd t0, EXCEPTION_KS0 csrrd t1, EXCEPTION_KS1 csrrd ra, EXCEPTION_KS2 ertn #ifdef CONFIG_64BIT vmalloc_modify: la.abs t1, swapper_pg_dir b vmalloc_done_modify #endif /* * This is the entry point when * build_tlbchange_handler_head spots a huge page. */ tlb_huge_update_modify: #ifdef CONFIG_SMP ll.d t0, t1, 0 #else ld.d t0, t1, 0 #endif srli.d ra, t0, _PAGE_WRITE_SHIFT andi ra, ra, 1 beqz ra, nopage_tlb_modify tlbsrch ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED) #ifdef CONFIG_SMP sc.d t0, t1, 0 beqz t0, tlb_huge_update_modify ld.d t0, t1, 0 #else st.d t0, t1, 0 #endif /* * A huge PTE describes an area the size of the * configured huge page size. This is twice the * of the large TLB entry size we intend to use. * A TLB entry half the size of the configured * huge page size is configured into entrylo0 * and entrylo1 to cover the contiguous huge PTE * address space. */ /* Huge page: Move Global bit */ xori t0, t0, _PAGE_HUGE lu12i.w t1, _PAGE_HGLOBAL >> 12 and t1, t0, t1 srli.d t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT) or t0, t0, t1 addi.d ra, t0, 0 csrwr t0, LOONGARCH_CSR_TLBELO0 addi.d t0, ra, 0 /* Convert to entrylo1 */ addi.d t1, zero, 1 slli.d t1, t1, (HPAGE_SHIFT - 1) add.d t0, t0, t1 csrwr t0, LOONGARCH_CSR_TLBELO1 /* Set huge page tlb entry size */ addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) addu16i.d t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) csrxchg t1, t0, LOONGARCH_CSR_TLBIDX tlbwr /* Reset default page size */ addu16i.d t0, zero, (CSR_TLBIDX_PS >> 16) addu16i.d t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16)) csrxchg t1, t0, LOONGARCH_CSR_TLBIDX nopage_tlb_modify: dbar 0 csrrd ra, EXCEPTION_KS2 la.abs t0, tlb_do_page_fault_1 jr t0 SYM_FUNC_END(handle_tlb_modify) SYM_FUNC_START(handle_tlb_refill) csrwr t0, LOONGARCH_CSR_TLBRSAVE csrrd t0, LOONGARCH_CSR_PGD lddir t0, t0, 3 #if CONFIG_PGTABLE_LEVELS > 3 lddir t0, t0, 2 #endif #if CONFIG_PGTABLE_LEVELS > 2 lddir t0, t0, 1 #endif ldpte t0, 0 ldpte t0, 1 tlbfill csrrd t0, LOONGARCH_CSR_TLBRSAVE ertn SYM_FUNC_END(handle_tlb_refill) |