[
    {
        "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)",
        "EventCode": "0x83",
        "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All",
        "PerPkg": "1",
        "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
        "Counter": "0,1",
        "EventCode": "0x84",
        "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
        "PerPkg": "1",
        "PublicDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
        "Counter": "0,",
        "CounterMask": "1",
        "EventCode": "0x80",
        "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
        "PerPkg": "1",
        "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.\n",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
        "PerPkg": "1",
        "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
        "UMask": "0x01",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
        "Counter": "0,1",
        "EventCode": "0x81",
        "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
        "PerPkg": "1",
        "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
        "UMask": "0x20",
        "Unit": "ARB"
    },
    {
        "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
        "Counter": "FIXED",
        "EventCode": "0xff",
        "EventName": "UNC_CLOCK.SOCKET",
        "PerPkg": "1",
        "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
        "Unit": "CLOCK"
    }
]