Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 | [ { "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.", "Counter": "0,1", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ALL", "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)", "SampleAfterValue": "200003" }, { "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", "Counter": "0,1", "EventCode": "0x86", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ", "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ALL", "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).", "SampleAfterValue": "200003" }, { "BriefDescription": "L2 cache request misses", "Counter": "0,1", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "L2 cache requests from this core", "Counter": "0,1", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.", "SampleAfterValue": "200003", "UMask": "0x4f" }, { "BriefDescription": "All Loads", "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PublicDescription": "This event counts the number of load ops retired.", "SampleAfterValue": "200003", "UMask": "0x40" }, { "BriefDescription": "All Stores", "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PublicDescription": "This event counts the number of store ops retired.", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Cross core or cross module hitm", "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.HITM", "PEBS": "1", "PublicDescription": "This event counts the number of load ops retired that got data from the other core or from the other module.", "SampleAfterValue": "200003", "UMask": "0x20" }, { "BriefDescription": "Loads missed L1", "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", "PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Loads hit L2", "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", "PEBS": "1", "PublicDescription": "This event counts the number of load ops retired that hit in the L2.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Loads missed L2", "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", "PEBS": "1", "PublicDescription": "This event counts the number of load ops retired that miss in the L2.", "SampleAfterValue": "100007", "UMask": "0x4" }, { "BriefDescription": "Loads missed UTLB", "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", "PublicDescription": "This event counts the number of load ops retired that had UTLB miss.", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010044", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000044", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000000044", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000044", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000044", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any data read (demand & prefetch) that have any response type.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000013091", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any data read (demand & prefetch) that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680003091", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000003091", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400003091", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200003091", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any request that have any response type.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000018008", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000008008", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400008008", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any request that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200008008", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010022", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000022", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000000022", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000022", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000022", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts writeback (modified to exclusive) that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000008", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0080000008", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010004", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000004", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000004", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000004", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x4000000004", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000010001", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch data read that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000001", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000000001", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000001", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000001", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x4000000001", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000002", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000000002", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000002", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000002", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "MSRValue": "0x4000000002", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000080", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000100", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0000012000", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680002000", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000002000", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400002000", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200002000", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000040", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000040", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000040", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000010", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000000010", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000010", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000010", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680000020", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1000000020", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0400000020", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x0200000020", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Counts streaming store that miss L2.", "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x1680004800", "Offcore": "1", "SampleAfterValue": "100007", "UMask": "0x1" }, { "BriefDescription": "Any reissued load uops", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.ANY_LD", "PublicDescription": "This event counts the number of load uops reissued from Rehabq.", "SampleAfterValue": "200003", "UMask": "0x40" }, { "BriefDescription": "Any reissued store uops", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.ANY_ST", "PublicDescription": "This event counts the number of store uops reissued from Rehabq.", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Loads blocked due to store data not ready", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", "PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Loads blocked due to store forward restriction", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", "PEBS": "1", "PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Load uops that split cache line boundary", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LD_SPLITS", "PEBS": "1", "PublicDescription": "This event counts the number of retire loads that experienced cache line boundary splits.", "SampleAfterValue": "200003", "UMask": "0x8" }, { "BriefDescription": "Uops with lock semantics", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LOCK", "PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).", "SampleAfterValue": "200003", "UMask": "0x10" }, { "BriefDescription": "Store address buffer full", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.STA_FULL", "PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.", "SampleAfterValue": "200003", "UMask": "0x20" }, { "BriefDescription": "Store uops that split cache line boundary", "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.ST_SPLITS", "PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.", "SampleAfterValue": "200003", "UMask": "0x4" } ] |