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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 | // SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. #include <linux/init.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/sched.h> #include <asm/mmu_context.h> #include <asm/setup.h> /* * One C-SKY MMU TLB entry contain two PFN/page entry, ie: * 1VPN -> 2PFN */ #define TLB_ENTRY_SIZE (PAGE_SIZE * 2) #define TLB_ENTRY_SIZE_MASK (PAGE_MASK << 1) void flush_tlb_all(void) { tlb_invalid_all(); } void flush_tlb_mm(struct mm_struct *mm) { #ifdef CONFIG_CPU_HAS_TLBI sync_is(); asm volatile( "tlbi.asids %0 \n" "sync.i \n" : : "r" (cpu_asid(mm)) : "memory"); #else tlb_invalid_all(); #endif } /* * MMU operation regs only could invalid tlb entry in jtlb and we * need change asid field to invalid I-utlb & D-utlb. */ #ifndef CONFIG_CPU_HAS_TLBI #define restore_asid_inv_utlb(oldpid, newpid) \ do { \ if (oldpid == newpid) \ write_mmu_entryhi(oldpid + 1); \ write_mmu_entryhi(oldpid); \ } while (0) #endif void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { unsigned long newpid = cpu_asid(vma->vm_mm); start &= TLB_ENTRY_SIZE_MASK; end += TLB_ENTRY_SIZE - 1; end &= TLB_ENTRY_SIZE_MASK; #ifdef CONFIG_CPU_HAS_TLBI sync_is(); while (start < end) { asm volatile( "tlbi.vas %0 \n" : : "r" (start | newpid) : "memory"); start += 2*PAGE_SIZE; } asm volatile("sync.i\n"); #else { unsigned long flags, oldpid; local_irq_save(flags); oldpid = read_mmu_entryhi() & ASID_MASK; while (start < end) { int idx; write_mmu_entryhi(start | newpid); start += 2*PAGE_SIZE; tlb_probe(); idx = read_mmu_index(); if (idx >= 0) tlb_invalid_indexed(); } restore_asid_inv_utlb(oldpid, newpid); local_irq_restore(flags); } #endif } void flush_tlb_kernel_range(unsigned long start, unsigned long end) { start &= TLB_ENTRY_SIZE_MASK; end += TLB_ENTRY_SIZE - 1; end &= TLB_ENTRY_SIZE_MASK; #ifdef CONFIG_CPU_HAS_TLBI sync_is(); while (start < end) { asm volatile( "tlbi.vaas %0 \n" : : "r" (start) : "memory"); start += 2*PAGE_SIZE; } asm volatile("sync.i\n"); #else { unsigned long flags, oldpid; local_irq_save(flags); oldpid = read_mmu_entryhi() & ASID_MASK; while (start < end) { int idx; write_mmu_entryhi(start | oldpid); start += 2*PAGE_SIZE; tlb_probe(); idx = read_mmu_index(); if (idx >= 0) tlb_invalid_indexed(); } restore_asid_inv_utlb(oldpid, oldpid); local_irq_restore(flags); } #endif } void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { int newpid = cpu_asid(vma->vm_mm); addr &= TLB_ENTRY_SIZE_MASK; #ifdef CONFIG_CPU_HAS_TLBI sync_is(); asm volatile( "tlbi.vas %0 \n" "sync.i \n" : : "r" (addr | newpid) : "memory"); #else { int oldpid, idx; unsigned long flags; local_irq_save(flags); oldpid = read_mmu_entryhi() & ASID_MASK; write_mmu_entryhi(addr | newpid); tlb_probe(); idx = read_mmu_index(); if (idx >= 0) tlb_invalid_indexed(); restore_asid_inv_utlb(oldpid, newpid); local_irq_restore(flags); } #endif } void flush_tlb_one(unsigned long addr) { addr &= TLB_ENTRY_SIZE_MASK; #ifdef CONFIG_CPU_HAS_TLBI sync_is(); asm volatile( "tlbi.vaas %0 \n" "sync.i \n" : : "r" (addr) : "memory"); #else { int oldpid, idx; unsigned long flags; local_irq_save(flags); oldpid = read_mmu_entryhi() & ASID_MASK; write_mmu_entryhi(addr | oldpid); tlb_probe(); idx = read_mmu_index(); if (idx >= 0) tlb_invalid_indexed(); restore_asid_inv_utlb(oldpid, oldpid); local_irq_restore(flags); } #endif } EXPORT_SYMBOL(flush_tlb_one); |