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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 | /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #ifndef _DPU_HW_SSPP_H #define _DPU_HW_SSPP_H #include "dpu_hw_catalog.h" #include "dpu_hw_mdss.h" #include "dpu_hw_util.h" #include "dpu_formats.h" struct dpu_hw_pipe; /** * Flags */ #define DPU_SSPP_FLIP_LR BIT(0) #define DPU_SSPP_FLIP_UD BIT(1) #define DPU_SSPP_SOURCE_ROTATED_90 BIT(2) #define DPU_SSPP_ROT_90 BIT(3) #define DPU_SSPP_SOLID_FILL BIT(4) /** * Define all scaler feature bits in catalog */ #define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \ BIT(DPU_SSPP_SCALER_QSEED2) | \ BIT(DPU_SSPP_SCALER_QSEED3) | \ BIT(DPU_SSPP_SCALER_QSEED3LITE) | \ BIT(DPU_SSPP_SCALER_QSEED4)) /* * Define all CSC feature bits in catalog */ #define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \ BIT(DPU_SSPP_CSC_10BIT)) /** * Component indices */ enum { DPU_SSPP_COMP_0, DPU_SSPP_COMP_1_2, DPU_SSPP_COMP_2, DPU_SSPP_COMP_3, DPU_SSPP_COMP_MAX }; /** * DPU_SSPP_RECT_SOLO - multirect disabled * DPU_SSPP_RECT_0 - rect0 of a multirect pipe * DPU_SSPP_RECT_1 - rect1 of a multirect pipe * * Note: HW supports multirect with either RECT0 or * RECT1. Considering no benefit of such configs over * SOLO mode and to keep the plane management simple, * we dont support single rect multirect configs. */ enum dpu_sspp_multirect_index { DPU_SSPP_RECT_SOLO = 0, DPU_SSPP_RECT_0, DPU_SSPP_RECT_1, }; enum dpu_sspp_multirect_mode { DPU_SSPP_MULTIRECT_NONE = 0, DPU_SSPP_MULTIRECT_PARALLEL, DPU_SSPP_MULTIRECT_TIME_MX, }; enum { DPU_FRAME_LINEAR, DPU_FRAME_TILE_A4X, DPU_FRAME_TILE_A5X, }; enum dpu_hw_filter { DPU_SCALE_FILTER_NEAREST = 0, DPU_SCALE_FILTER_BIL, DPU_SCALE_FILTER_PCMN, DPU_SCALE_FILTER_CA, DPU_SCALE_FILTER_MAX }; enum dpu_hw_filter_alpa { DPU_SCALE_ALPHA_PIXEL_REP, DPU_SCALE_ALPHA_BIL }; enum dpu_hw_filter_yuv { DPU_SCALE_2D_4X4, DPU_SCALE_2D_CIR, DPU_SCALE_1D_SEP, DPU_SCALE_BIL }; struct dpu_hw_sharp_cfg { u32 strength; u32 edge_thr; u32 smooth_thr; u32 noise_thr; }; struct dpu_hw_pixel_ext { /* scaling factors are enabled for this input layer */ uint8_t enable_pxl_ext; int init_phase_x[DPU_MAX_PLANES]; int phase_step_x[DPU_MAX_PLANES]; int init_phase_y[DPU_MAX_PLANES]; int phase_step_y[DPU_MAX_PLANES]; /* * Number of pixels extension in left, right, top and bottom direction * for all color components. This pixel value for each color component * should be sum of fetch + repeat pixels. */ int num_ext_pxls_left[DPU_MAX_PLANES]; int num_ext_pxls_right[DPU_MAX_PLANES]; int num_ext_pxls_top[DPU_MAX_PLANES]; int num_ext_pxls_btm[DPU_MAX_PLANES]; /* * Number of pixels needs to be overfetched in left, right, top and * bottom directions from source image for scaling. */ int left_ftch[DPU_MAX_PLANES]; int right_ftch[DPU_MAX_PLANES]; int top_ftch[DPU_MAX_PLANES]; int btm_ftch[DPU_MAX_PLANES]; /* * Number of pixels needs to be repeated in left, right, top and * bottom directions for scaling. */ int left_rpt[DPU_MAX_PLANES]; int right_rpt[DPU_MAX_PLANES]; int top_rpt[DPU_MAX_PLANES]; int btm_rpt[DPU_MAX_PLANES]; uint32_t roi_w[DPU_MAX_PLANES]; uint32_t roi_h[DPU_MAX_PLANES]; /* * Filter type to be used for scaling in horizontal and vertical * directions */ enum dpu_hw_filter horz_filter[DPU_MAX_PLANES]; enum dpu_hw_filter vert_filter[DPU_MAX_PLANES]; }; /** * struct dpu_hw_pipe_cfg : Pipe description * @layout: format layout information for programming buffer to hardware * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. * @index: index of the rectangle of SSPP * @mode: parallel or time multiplex multirect mode */ struct dpu_hw_pipe_cfg { struct dpu_hw_fmt_layout layout; struct drm_rect src_rect; struct drm_rect dst_rect; enum dpu_sspp_multirect_index index; enum dpu_sspp_multirect_mode mode; }; /** * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration * @creq_vblank: creq value generated to vbif during vertical blanking * @danger_vblank: danger value generated during vertical blanking * @vblank_en: enable creq_vblank and danger_vblank during vblank * @danger_safe_en: enable danger safe generation */ struct dpu_hw_pipe_qos_cfg { u32 creq_vblank; u32 danger_vblank; bool vblank_en; bool danger_safe_en; }; /** * enum CDP preload ahead address size */ enum { DPU_SSPP_CDP_PRELOAD_AHEAD_32, DPU_SSPP_CDP_PRELOAD_AHEAD_64 }; /** * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration * @size: size to prefill in bytes, or zero to disable * @time: time to prefill in usec, or zero to disable */ struct dpu_hw_pipe_ts_cfg { u64 size; u64 time; }; /** * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions * Caller must call the init function to get the pipe context for each pipe * Assumption is these functions will be called after clocks are enabled */ struct dpu_hw_sspp_ops { /** * setup_format - setup pixel format cropping rectangle, flip * @ctx: Pointer to pipe context * @cfg: Pointer to pipe config structure * @flags: Extra flags for format config * @index: rectangle index in multirect */ void (*setup_format)(struct dpu_hw_pipe *ctx, const struct dpu_format *fmt, u32 flags, enum dpu_sspp_multirect_index index); /** * setup_rects - setup pipe ROI rectangles * @ctx: Pointer to pipe context * @cfg: Pointer to pipe config structure * @index: rectangle index in multirect */ void (*setup_rects)(struct dpu_hw_pipe *ctx, struct dpu_hw_pipe_cfg *cfg, enum dpu_sspp_multirect_index index); /** * setup_pe - setup pipe pixel extension * @ctx: Pointer to pipe context * @pe_ext: Pointer to pixel ext settings */ void (*setup_pe)(struct dpu_hw_pipe *ctx, struct dpu_hw_pixel_ext *pe_ext); /** * setup_sourceaddress - setup pipe source addresses * @ctx: Pointer to pipe context * @cfg: Pointer to pipe config structure * @index: rectangle index in multirect */ void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx, struct dpu_hw_pipe_cfg *cfg, enum dpu_sspp_multirect_index index); /** * setup_csc - setup color space coversion * @ctx: Pointer to pipe context * @data: Pointer to config structure */ void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data); /** * setup_solidfill - enable/disable colorfill * @ctx: Pointer to pipe context * @const_color: Fill color value * @flags: Pipe flags * @index: rectangle index in multirect */ void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color, enum dpu_sspp_multirect_index index); /** * setup_multirect - setup multirect configuration * @ctx: Pointer to pipe context * @index: rectangle index in multirect * @mode: parallel fetch / time multiplex multirect mode */ void (*setup_multirect)(struct dpu_hw_pipe *ctx, enum dpu_sspp_multirect_index index, enum dpu_sspp_multirect_mode mode); /** * setup_sharpening - setup sharpening * @ctx: Pointer to pipe context * @cfg: Pointer to config structure */ void (*setup_sharpening)(struct dpu_hw_pipe *ctx, struct dpu_hw_sharp_cfg *cfg); /** * setup_danger_safe_lut - setup danger safe LUTs * @ctx: Pointer to pipe context * @danger_lut: LUT for generate danger level based on fill level * @safe_lut: LUT for generate safe level based on fill level * */ void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx, u32 danger_lut, u32 safe_lut); /** * setup_creq_lut - setup CREQ LUT * @ctx: Pointer to pipe context * @creq_lut: LUT for generate creq level based on fill level * */ void (*setup_creq_lut)(struct dpu_hw_pipe *ctx, u64 creq_lut); /** * setup_qos_ctrl - setup QoS control * @ctx: Pointer to pipe context * @cfg: Pointer to pipe QoS configuration * */ void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx, struct dpu_hw_pipe_qos_cfg *cfg); /** * setup_histogram - setup histograms * @ctx: Pointer to pipe context * @cfg: Pointer to histogram configuration */ void (*setup_histogram)(struct dpu_hw_pipe *ctx, void *cfg); /** * setup_scaler - setup scaler * @ctx: Pointer to pipe context * @pipe_cfg: Pointer to pipe configuration * @scaler_cfg: Pointer to scaler configuration */ void (*setup_scaler)(struct dpu_hw_pipe *ctx, struct dpu_hw_pipe_cfg *pipe_cfg, void *scaler_cfg); /** * get_scaler_ver - get scaler h/w version * @ctx: Pointer to pipe context */ u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx); /** * setup_cdp - setup client driven prefetch * @ctx: Pointer to pipe context * @cfg: Pointer to cdp configuration * @index: rectangle index in multirect */ void (*setup_cdp)(struct dpu_hw_pipe *ctx, struct dpu_hw_cdp_cfg *cfg, enum dpu_sspp_multirect_index index); }; /** * struct dpu_hw_pipe - pipe description * @base: hardware block base structure * @hw: block hardware details * @catalog: back pointer to catalog * @mdp: pointer to associated mdp portion of the catalog * @idx: pipe index * @cap: pointer to layer_cfg * @ops: pointer to operations possible for this pipe */ struct dpu_hw_pipe { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; const struct dpu_mdss_cfg *catalog; const struct dpu_mdp_cfg *mdp; /* Pipe */ enum dpu_sspp idx; const struct dpu_sspp_cfg *cap; /* Ops */ struct dpu_hw_sspp_ops ops; }; struct dpu_kms; /** * dpu_hw_sspp_init - initializes the sspp hw driver object. * Should be called once before accessing every pipe. * @idx: Pipe index for which driver object is required * @addr: Mapped register io address of MDP * @catalog : Pointer to mdss catalog data * @is_virtual_pipe: is this pipe virtual pipe */ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, const struct dpu_mdss_cfg *catalog, bool is_virtual_pipe); /** * dpu_hw_sspp_destroy(): Destroys SSPP driver context * should be called during Hw pipe cleanup. * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init */ void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx); void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root); int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry); #endif /*_DPU_HW_SSPP_H */ |