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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Marvell 88E6xxx System Management Interface (SMI) support * * Copyright (c) 2008 Marvell Semiconductor * * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com> */ #include "chip.h" #include "smi.h" /* The switch ADDR[4:1] configuration pins define the chip SMI device address * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). * * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it * is the only device connected to the SMI master. In this mode it responds to * all 32 possible SMI addresses, and thus maps directly the internal devices. * * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing * multiple devices to share the SMI interface. In this mode it responds to only * 2 registers, used to indirectly access the internal SMI devices. * * Some chips use a different scheme: Only the ADDR4 pin is used for * configuration, and the device responds to 16 of the 32 SMI * addresses, allowing two to coexist on the same SMI interface. */ static int mv88e6xxx_smi_direct_read(struct mv88e6xxx_chip *chip, int dev, int reg, u16 *data) { int ret; ret = mdiobus_read_nested(chip->bus, dev, reg); if (ret < 0) return ret; *data = ret & 0xffff; return 0; } static int mv88e6xxx_smi_direct_write(struct mv88e6xxx_chip *chip, int dev, int reg, u16 data) { int ret; ret = mdiobus_write_nested(chip->bus, dev, reg, data); if (ret < 0) return ret; return 0; } static int mv88e6xxx_smi_direct_wait(struct mv88e6xxx_chip *chip, int dev, int reg, int bit, int val) { u16 data; int err; int i; for (i = 0; i < 16; i++) { err = mv88e6xxx_smi_direct_read(chip, dev, reg, &data); if (err) return err; if (!!(data & BIT(bit)) == !!val) return 0; usleep_range(1000, 2000); } return -ETIMEDOUT; } static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_direct_ops = { .read = mv88e6xxx_smi_direct_read, .write = mv88e6xxx_smi_direct_write, }; static int mv88e6xxx_smi_dual_direct_read(struct mv88e6xxx_chip *chip, int dev, int reg, u16 *data) { return mv88e6xxx_smi_direct_read(chip, chip->sw_addr + dev, reg, data); } static int mv88e6xxx_smi_dual_direct_write(struct mv88e6xxx_chip *chip, int dev, int reg, u16 data) { return mv88e6xxx_smi_direct_write(chip, chip->sw_addr + dev, reg, data); } static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_dual_direct_ops = { .read = mv88e6xxx_smi_dual_direct_read, .write = mv88e6xxx_smi_dual_direct_write, }; /* Offset 0x00: SMI Command Register * Offset 0x01: SMI Data Register */ static int mv88e6xxx_smi_indirect_read(struct mv88e6xxx_chip *chip, int dev, int reg, u16 *data) { int err; err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, MV88E6XXX_SMI_CMD, 15, 0); if (err) return err; err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, MV88E6XXX_SMI_CMD, MV88E6XXX_SMI_CMD_BUSY | MV88E6XXX_SMI_CMD_MODE_22 | MV88E6XXX_SMI_CMD_OP_22_READ | (dev << 5) | reg); if (err) return err; err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, MV88E6XXX_SMI_CMD, 15, 0); if (err) return err; return mv88e6xxx_smi_direct_read(chip, chip->sw_addr, MV88E6XXX_SMI_DATA, data); } static int mv88e6xxx_smi_indirect_write(struct mv88e6xxx_chip *chip, int dev, int reg, u16 data) { int err; err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, MV88E6XXX_SMI_CMD, 15, 0); if (err) return err; err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, MV88E6XXX_SMI_DATA, data); if (err) return err; err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr, MV88E6XXX_SMI_CMD, MV88E6XXX_SMI_CMD_BUSY | MV88E6XXX_SMI_CMD_MODE_22 | MV88E6XXX_SMI_CMD_OP_22_WRITE | (dev << 5) | reg); if (err) return err; return mv88e6xxx_smi_direct_wait(chip, chip->sw_addr, MV88E6XXX_SMI_CMD, 15, 0); } static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_indirect_ops = { .read = mv88e6xxx_smi_indirect_read, .write = mv88e6xxx_smi_indirect_write, }; int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, struct mii_bus *bus, int sw_addr) { if (chip->info->dual_chip) chip->smi_ops = &mv88e6xxx_smi_dual_direct_ops; else if (sw_addr == 0) chip->smi_ops = &mv88e6xxx_smi_direct_ops; else if (chip->info->multi_chip) chip->smi_ops = &mv88e6xxx_smi_indirect_ops; else return -EINVAL; chip->bus = bus; chip->sw_addr = sw_addr; return 0; } |