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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 | /* * Toshiba rbtx4927 specific setup * * Author: MontaVista Software, Inc. * source@mvista.com * * Copyright 2001-2002 MontaVista Software Inc. * * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2000 RidgeRun, Inc. * Author: RidgeRun, Inc. * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com * * Copyright 2001 MontaVista Software Inc. * Author: jsun@mvista.com or jsun@junsun.net * * Copyright 2002 MontaVista Software Inc. * Author: Michael Pruznick, michael_pruznick@mvista.com * * Copyright (C) 2000-2001 Toshiba Corporation * * Copyright (C) 2004 MontaVista Software Inc. * Author: Manish Lachwani, mlachwani@mvista.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/init.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/ioport.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/gpio.h> #include <linux/leds.h> #include <asm/io.h> #include <asm/reboot.h> #include <asm/txx9pio.h> #include <asm/txx9/generic.h> #include <asm/txx9/pci.h> #include <asm/txx9/rbtx4927.h> #include <asm/txx9/tx4938.h> /* for TX4937 */ #ifdef CONFIG_PCI static void __init tx4927_pci_setup(void) { int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); struct pci_controller *c = &txx9_primary_pcic; register_pci_controller(c); if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) txx9_pci_option = (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | TXX9_PCI_OPT_CLK_66; /* already configured */ /* Reset PCI Bus */ writeb(1, rbtx4927_pcireset_addr); /* Reset PCIC */ txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == TXX9_PCI_OPT_CLK_66) tx4927_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); writeb(0, rbtx4927_pcireset_addr); iob(); tx4927_report_pciclk(); tx4927_pcic_setup(tx4927_pcicptr, c, extarb); if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == TXX9_PCI_OPT_CLK_AUTO && txx9_pci66_check(c, 0, 0)) { /* Reset PCI Bus */ writeb(1, rbtx4927_pcireset_addr); /* Reset PCIC */ txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); tx4927_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); writeb(0, rbtx4927_pcireset_addr); iob(); /* Reinitialize PCIC */ tx4927_report_pciclk(); tx4927_pcic_setup(tx4927_pcicptr, c, extarb); } tx4927_setup_pcierr_irq(); } static void __init tx4937_pci_setup(void) { int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); struct pci_controller *c = &txx9_primary_pcic; register_pci_controller(c); if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) txx9_pci_option = (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | TXX9_PCI_OPT_CLK_66; /* already configured */ /* Reset PCI Bus */ writeb(1, rbtx4927_pcireset_addr); /* Reset PCIC */ txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == TXX9_PCI_OPT_CLK_66) tx4938_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); writeb(0, rbtx4927_pcireset_addr); iob(); tx4938_report_pciclk(); tx4927_pcic_setup(tx4938_pcicptr, c, extarb); if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == TXX9_PCI_OPT_CLK_AUTO && txx9_pci66_check(c, 0, 0)) { /* Reset PCI Bus */ writeb(1, rbtx4927_pcireset_addr); /* Reset PCIC */ txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); tx4938_pciclk66_setup(); mdelay(10); /* clear PCIC reset */ txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); writeb(0, rbtx4927_pcireset_addr); iob(); /* Reinitialize PCIC */ tx4938_report_pciclk(); tx4927_pcic_setup(tx4938_pcicptr, c, extarb); } tx4938_setup_pcierr_irq(); } #else static inline void tx4927_pci_setup(void) {} static inline void tx4937_pci_setup(void) {} #endif /* CONFIG_PCI */ static void __init rbtx4927_gpio_init(void) { /* TX4927-SIO DTR on (PIO[15]) */ gpio_request(15, "sio-dtr"); gpio_direction_output(15, 1); tx4927_sio_init(0, 0); } static void __init rbtx4927_arch_init(void) { txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO); rbtx4927_gpio_init(); tx4927_pci_setup(); } static void __init rbtx4937_arch_init(void) { txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO); rbtx4927_gpio_init(); tx4937_pci_setup(); } static void toshiba_rbtx4927_restart(char *command) { /* enable the s/w reset register */ writeb(1, rbtx4927_softresetlock_addr); /* wait for enable to be seen */ while (!(readb(rbtx4927_softresetlock_addr) & 1)) ; /* do a s/w reset */ writeb(1, rbtx4927_softreset_addr); /* fallback */ (*_machine_halt)(); } static void __init rbtx4927_clock_init(void); static void __init rbtx4937_clock_init(void); static void __init rbtx4927_mem_setup(void) { if (TX4927_REV_PCODE() == 0x4927) { rbtx4927_clock_init(); tx4927_setup(); } else { rbtx4937_clock_init(); tx4938_setup(); } _machine_restart = toshiba_rbtx4927_restart; #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); #endif } static void __init rbtx4927_clock_init(void) { /* * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. * * For TX4927: * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) * i.e. S9[3]: ON (83MHz), OFF (100MHz) */ switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIDIVMODE_MASK) { case TX4927_CCFG_PCIDIVMODE_2_5: case TX4927_CCFG_PCIDIVMODE_5: txx9_cpu_clock = 166666666; /* 166MHz */ break; default: txx9_cpu_clock = 200000000; /* 200MHz */ } } static void __init rbtx4937_clock_init(void) { /* * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. * * For TX4937: * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) * PCIDIVMODE[10] is 0. * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) */ switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIDIVMODE_MASK) { case TX4938_CCFG_PCIDIVMODE_8: case TX4938_CCFG_PCIDIVMODE_4: txx9_cpu_clock = 266666666; /* 266MHz */ break; case TX4938_CCFG_PCIDIVMODE_9: case TX4938_CCFG_PCIDIVMODE_4_5: txx9_cpu_clock = 300000000; /* 300MHz */ break; default: txx9_cpu_clock = 333333333; /* 333MHz */ } } static void __init rbtx4927_time_init(void) { tx4927_time_init(0); } static void __init toshiba_rbtx4927_rtc_init(void) { struct resource res = { .start = RBTX4927_BRAMRTC_BASE - IO_BASE, .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, .flags = IORESOURCE_MEM, }; platform_device_register_simple("rtc-ds1742", -1, &res, 1); } static void __init rbtx4927_ne_init(void) { struct resource res[] = { { .start = RBTX4927_RTL_8019_BASE, .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, .flags = IORESOURCE_IO, }, { .start = RBTX4927_RTL_8019_IRQ, .flags = IORESOURCE_IRQ, } }; platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res)); } static void __init rbtx4927_mtd_init(void) { int i; for (i = 0; i < 2; i++) tx4927_mtd_init(i); } static void __init rbtx4927_gpioled_init(void) { static const struct gpio_led leds[] = { { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, }, { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, }, }; static struct gpio_led_platform_data pdata = { .num_leds = ARRAY_SIZE(leds), .leds = leds, }; struct platform_device *pdev = platform_device_alloc("leds-gpio", 0); if (!pdev) return; pdev->dev.platform_data = &pdata; if (platform_device_add(pdev)) platform_device_put(pdev); } static void __init rbtx4927_device_init(void) { toshiba_rbtx4927_rtc_init(); rbtx4927_ne_init(); tx4927_wdt_init(); rbtx4927_mtd_init(); if (TX4927_REV_PCODE() == 0x4927) { tx4927_dmac_init(2); tx4927_aclc_init(0, 1); } else { tx4938_dmac_init(0, 2); tx4938_aclc_init(); } platform_device_register_simple("txx9aclc-generic", -1, NULL, 0); txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); rbtx4927_gpioled_init(); } struct txx9_board_vec rbtx4927_vec __initdata = { .system = "Toshiba RBTX4927", .prom_init = rbtx4927_prom_init, .mem_setup = rbtx4927_mem_setup, .irq_setup = rbtx4927_irq_setup, .time_init = rbtx4927_time_init, .device_init = rbtx4927_device_init, .arch_init = rbtx4927_arch_init, #ifdef CONFIG_PCI .pci_map_irq = rbtx4927_pci_map_irq, #endif }; struct txx9_board_vec rbtx4937_vec __initdata = { .system = "Toshiba RBTX4937", .prom_init = rbtx4927_prom_init, .mem_setup = rbtx4927_mem_setup, .irq_setup = rbtx4927_irq_setup, .time_init = rbtx4927_time_init, .device_init = rbtx4927_device_init, .arch_init = rbtx4937_arch_init, #ifdef CONFIG_PCI .pci_map_irq = rbtx4927_pci_map_irq, #endif }; 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