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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 | // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8994.h> / { model = "Qualcomm Technologies, Inc. MSM 8992"; compatible = "qcom,msm8992"; // msm-id needed by bootloader for selecting correct blob qcom,msm-id = <251 0>, <252 0>; interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; chosen { }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; }; }; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; xo_board: xo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; }; sleep_clk: sleep_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; vreg_vph_pwr: vreg-vph-pwr { compatible = "regulator-fixed"; status = "okay"; regulator-name = "vph-pwr"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; regulator-always-on; }; sfpb_mutex: hwmutex { compatible = "qcom,sfpb-mutex"; syscon = <&sfpb_mutex_regs 0x0 0x100>; #hwlock-cells = <1>; }; smem { compatible = "qcom,smem"; memory-region = <&smem_region>; qcom,rpm-msg-ram = <&rpm_msg_ram>; hwlocks = <&sfpb_mutex 3>; }; soc { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; intc: interrupt-controller@f9000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; #interrupt-cells = <3>; reg = <0xf9000000 0x1000>, <0xf9002000 0x1000>; }; apcs: syscon@f900d000 { compatible = "syscon"; reg = <0xf900d000 0x2000>; }; timer@f9020000 { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "arm,armv7-timer-mem"; reg = <0xf9020000 0x1000>; frame@f9021000 { frame-number = <0>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9021000 0x1000>, <0xf9022000 0x1000>; }; frame@f9023000 { frame-number = <1>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9023000 0x1000>; status = "disabled"; }; frame@f9024000 { frame-number = <2>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9024000 0x1000>; status = "disabled"; }; frame@f9025000 { frame-number = <3>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9025000 0x1000>; status = "disabled"; }; frame@f9026000 { frame-number = <4>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9026000 0x1000>; status = "disabled"; }; frame@f9027000 { frame-number = <5>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9027000 0x1000>; status = "disabled"; }; frame@f9028000 { frame-number = <6>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9028000 0x1000>; status = "disabled"; }; }; restart@fc4ab000 { compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; }; msmgpio: pinctrl@fd510000 { compatible = "qcom,msm8994-pinctrl"; reg = <0xfd510000 0x4000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; gpio-ranges = <&msmgpio 0 0 146>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>; status = "disabled"; clock-names = "core", "iface"; clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; }; clock_gcc: clock-controller@fc400000 { compatible = "qcom,gcc-msm8994"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; }; sdhci1: mmc@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>, <GIC_SPI 138 IRQ_TYPE_NONE>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; regulator-always-on; bus-width = <8>; mmc-hs400-1_8v; status = "okay"; }; rpm_msg_ram: memory@fc428000 { compatible = "qcom,rpm-msg-ram"; reg = <0xfc428000 0x4000>; }; sfpb_mutex_regs: syscon@fd484000 { #address-cells = <1>; #size-cells = <1>; compatible = "syscon"; reg = <0xfd484000 0x400>; }; }; memory { device_type = "memory"; reg = <0 0 0 0>; // bootloader will update }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; smem_region: smem@6a00000 { reg = <0x0 0x6a00000 0x0 0x200000>; no-map; }; }; smd_rpm: smd { compatible = "qcom,smd"; rpm { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; qcom,local-pid = <0>; qcom,remote-pid = <6>; rpm-requests { compatible = "qcom,rpm-msm8994"; qcom,smd-channels = "rpm_requests"; pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; pm8994_s1: s1 {}; pm8994_s2: s2 {}; pm8994_s3: s3 {}; pm8994_s4: s4 {}; pm8994_s5: s5 {}; pm8994_s6: s6 {}; pm8994_s7: s7 {}; pm8994_l1: l1 {}; pm8994_l2: l2 {}; pm8994_l3: l3 {}; pm8994_l4: l4 {}; pm8994_l6: l6 {}; pm8994_l8: l8 {}; pm8994_l9: l9 {}; pm8994_l10: l10 {}; pm8994_l11: l11 {}; pm8994_l12: l12 {}; pm8994_l13: l13 {}; pm8994_l14: l14 {}; pm8994_l15: l15 {}; pm8994_l16: l16 {}; pm8994_l17: l17 {}; pm8994_l18: l18 {}; pm8994_l19: l19 {}; pm8994_l20: l20 {}; pm8994_l21: l21 {}; pm8994_l22: l22 {}; pm8994_l23: l23 {}; pm8994_l24: l24 {}; pm8994_l25: l25 {}; pm8994_l26: l26 {}; pm8994_l27: l27 {}; pm8994_l28: l28 {}; pm8994_l29: l29 {}; pm8994_l30: l30 {}; pm8994_l31: l31 {}; pm8994_l32: l32 {}; pm8994_lvs1: lvs1 {}; pm8994_lvs2: lvs2 {}; }; }; }; }; }; #include "msm8992-pins.dtsi" |