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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 | // SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2014 Carlo Caione <carlo@caione.org> */ #include <dt-bindings/clock/meson8-ddr-clkc.h> #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include <dt-bindings/reset/amlogic,meson8b-reset.h> #include "meson.dtsi" / { model = "Amlogic Meson8 SoC"; compatible = "amlogic,meson8"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x200>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPUCLK>; }; cpu1: cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x201>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPUCLK>; }; cpu2: cpu@202 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x202>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPUCLK>; }; cpu3: cpu@203 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x203>; enable-method = "amlogic,meson8-smp"; resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPUCLK>; }; }; cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; opp-96000000 { opp-hz = /bits/ 64 <96000000>; opp-microvolt = <825000>; }; opp-192000000 { opp-hz = /bits/ 64 <192000000>; opp-microvolt = <825000>; }; opp-312000000 { opp-hz = /bits/ 64 <312000000>; opp-microvolt = <825000>; }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <825000>; }; opp-504000000 { opp-hz = /bits/ 64 <504000000>; opp-microvolt = <825000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <850000>; }; opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <850000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <875000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <925000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <975000>; }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <1025000>; }; opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <1100000>; }; opp-1800000000 { status = "disabled"; opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1125000>; }; opp-1992000000 { status = "disabled"; opp-hz = /bits/ 64 <1992000000>; opp-microvolt = <1150000>; }; }; gpu_opp_table: gpu-opp-table { compatible = "operating-points-v2"; opp-182142857 { opp-hz = /bits/ 64 <182142857>; opp-microvolt = <1150000>; }; opp-318750000 { opp-hz = /bits/ 64 <318750000>; opp-microvolt = <1150000>; }; opp-425000000 { opp-hz = /bits/ 64 <425000000>; opp-microvolt = <1150000>; }; opp-510000000 { opp-hz = /bits/ 64 <510000000>; opp-microvolt = <1150000>; }; opp-637500000 { opp-hz = /bits/ 64 <637500000>; opp-microvolt = <1150000>; turbo-mode; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; /* 2 MiB reserved for Hardware ROM Firmware? */ hwrom@0 { reg = <0x0 0x200000>; no-map; }; /* * 1 MiB reserved for the "ARM Power Firmware": this is ARM * code which is responsible for system suspend. It loads a * piece of ARC code ("arc_power" in the vendor u-boot tree) * into SRAM, executes that and shuts down the (last) ARM core. * The arc_power firmware then checks various wakeup sources * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or * simply the power key) and re-starts the ARM core once it * detects a wakeup request. */ power-firmware@4f00000 { reg = <0x4f00000 0x100000>; no-map; }; }; mmcbus: bus@c8000000 { compatible = "simple-bus"; reg = <0xc8000000 0x8000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xc8000000 0x8000>; ddr_clkc: clock-controller@400 { compatible = "amlogic,meson8-ddr-clkc"; reg = <0x400 0x20>; clocks = <&xtal>; clock-names = "xtal"; #clock-cells = <1>; }; dmcbus: bus@6000 { compatible = "simple-bus"; reg = <0x6000 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x6000 0x400>; canvas: video-lut@20 { compatible = "amlogic,meson8-canvas", "amlogic,canvas"; reg = <0x20 0x14>; }; }; }; apb: bus@d0000000 { compatible = "simple-bus"; reg = <0xd0000000 0x200000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000000 0x200000>; mali: gpu@c0000 { compatible = "amlogic,meson8-mali", "arm,mali-450"; reg = <0xc0000 0x40000>; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp", "pmu", "pp0", "ppmmu0", "pp1", "ppmmu1", "pp2", "ppmmu2", "pp4", "ppmmu4", "pp5", "ppmmu5", "pp6", "ppmmu6"; resets = <&reset RESET_MALI>; clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; clock-names = "bus", "core"; operating-points-v2 = <&gpu_opp_table>; }; }; }; /* end of / */ &aobus { pmu: pmu@e0 { compatible = "amlogic,meson8-pmu", "syscon"; reg = <0xe0 0x18>; }; pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8-aobus-pinctrl"; reg = <0x84 0xc>; #address-cells = <1>; #size-cells = <1>; ranges; gpio_ao: ao-bank@14 { reg = <0x14 0x4>, <0x2c 0x4>, <0x24 0x8>; reg-names = "mux", "pull", "gpio"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_aobus 0 0 16>; }; uart_ao_a_pins: uart_ao_a { mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; bias-disable; }; }; i2c_ao_pins: i2c_mst_ao { mux { groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; function = "i2c_mst_ao"; bias-disable; }; }; ir_recv_pins: remote { mux { groups = "remote_input"; function = "remote"; bias-disable; }; }; pwm_f_ao_pins: pwm-f-ao { mux { groups = "pwm_f_ao"; function = "pwm_f_ao"; bias-disable; }; }; }; }; &cbus { reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; #reset-cells = <1>; }; analog_top: analog-top@81a8 { compatible = "amlogic,meson8-analog-top", "syscon"; reg = <0x81a8 0x14>; }; pwm_ef: pwm@86c0 { compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; reg = <0x86c0 0x10>; #pwm-cells = <3>; status = "disabled"; }; clock-measure@8758 { compatible = "amlogic,meson8-clk-measure"; reg = <0x8758 0x1c>; }; pinctrl_cbus: pinctrl@9880 { compatible = "amlogic,meson8-cbus-pinctrl"; reg = <0x9880 0x10>; #address-cells = <1>; #size-cells = <1>; ranges; gpio: banks@80b0 { reg = <0x80b0 0x28>, <0x80e8 0x18>, <0x8120 0x18>, <0x8030 0x30>; reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl_cbus 0 0 120>; }; sd_a_pins: sd-a { mux { groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"; function = "sd_a"; bias-disable; }; }; sd_b_pins: sd-b { mux { groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", "sd_d3_b", "sd_clk_b", "sd_cmd_b"; function = "sd_b"; bias-disable; }; }; sd_c_pins: sd-c { mux { groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", "sd_clk_c", "sd_cmd_c"; function = "sd_c"; bias-disable; }; }; spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs"; function = "nor"; bias-disable; }; }; eth_pins: ethernet { mux { groups = "eth_tx_clk_50m", "eth_tx_en", "eth_txd1", "eth_txd0", "eth_rx_clk_in", "eth_rx_dv", "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"; function = "ethernet"; bias-disable; }; }; pwm_e_pins: pwm-e { mux { groups = "pwm_e"; function = "pwm_e"; bias-disable; }; }; uart_a1_pins: uart-a1 { mux { groups = "uart_tx_a1", "uart_rx_a1"; function = "uart_a"; bias-disable; }; }; uart_a1_cts_rts_pins: uart-a1-cts-rts { mux { groups = "uart_cts_a1", "uart_rts_a1"; function = "uart_a"; bias-disable; }; }; }; }; &ahb_sram { smp-sram@1ff80 { compatible = "amlogic,meson8-smp-sram"; reg = <0x1ff80 0x8>; }; }; &efuse { compatible = "amlogic,meson8-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; temperature_calib: calib@1f4 { /* only the upper two bytes are relevant */ reg = <0x1f4 0x4>; }; }; ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; }; &gpio_intc { compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; status = "okay"; }; &hhi { clkc: clock-controller { compatible = "amlogic,meson8-clkc"; clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; clock-names = "xtal", "ddr_pll"; #clock-cells = <1>; #reset-cells = <1>; }; }; &hwrng { compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; clock-names = "core"; }; &i2c_AO { clocks = <&clkc CLKID_CLK81>; }; &i2c_A { clocks = <&clkc CLKID_CLK81>; }; &i2c_B { clocks = <&clkc CLKID_CLK81>; }; &L2 { arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; arm,filter-ranges = <0x100000 0xc0000000>; prefetch-data = <1>; prefetch-instr = <1>; arm,shared-override; }; &periph { scu@0 { compatible = "arm,cortex-a9-scu"; reg = <0x0 0x100>; }; timer@200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x200 0x20>; interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; clocks = <&clkc CLKID_PERIPH>; /* * the arm_global_timer driver currently does not handle clock * rate changes. Keep it disabled for now. */ status = "disabled"; }; timer@600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x600 0x20>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; clocks = <&clkc CLKID_PERIPH>; }; }; &pwm_ab { compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; }; &pwm_cd { compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; }; &rtc { compatible = "amlogic,meson8-rtc"; resets = <&reset RESET_RTC>; }; &saradc { compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; amlogic,hhi-sysctrl = <&hhi>; nvmem-cells = <&temperature_calib>; nvmem-cell-names = "temperature_calib"; }; &sdio { compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; clock-names = "core", "clkin"; }; &spifc { clocks = <&clkc CLKID_CLK81>; }; &timer_abcde { clocks = <&xtal>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk"; }; &uart_AO { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>; clock-names = "baud", "xtal", "pclk"; }; &uart_A { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>; clock-names = "baud", "xtal", "pclk"; }; &uart_B { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>; clock-names = "baud", "xtal", "pclk"; }; &uart_C { compatible = "amlogic,meson8-uart", "amlogic,meson-uart"; clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>; clock-names = "baud", "xtal", "pclk"; }; &usb0 { compatible = "amlogic,meson8-usb", "snps,dwc2"; clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; clock-names = "otg"; }; &usb1 { compatible = "amlogic,meson8-usb", "snps,dwc2"; clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; clock-names = "otg"; }; &usb0_phy { compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; clock-names = "usb_general", "usb"; resets = <&reset RESET_USB_OTG>; }; &usb1_phy { compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; clock-names = "usb_general", "usb"; resets = <&reset RESET_USB_OTG>; }; |