* UART (Universal Asynchronous Receiver/Transmitter)

Required properties:
- compatible : one of:
	- "ns8250"
	- "ns16450"
	- "ns16550a"
	- "ns16550"
	- "ns16750"
	- "ns16850"
	- For Tegra20, must contain "nvidia,tegra20-uart"
	- For other Tegra, must contain '"nvidia,<chip>-uart",
	  "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
	  tegra132, or tegra210.
	- "nxp,lpc3220-uart"
	- "ralink,rt2880-uart"
	- For MediaTek BTIF, must contain '"mediatek,<chip>-btif",
	  "mediatek,mtk-btif"' where <chip> is mt7622, mt7623.
	- "altr,16550-FIFO32"
	- "altr,16550-FIFO64"
	- "altr,16550-FIFO128"
	- "fsl,16550-FIFO64"
	- "fsl,ns16550"
	- "intel,xscale-uart"
	- "ti,da830-uart"
	- "aspeed,ast2400-vuart"
	- "aspeed,ast2500-vuart"
	- "nuvoton,npcm750-uart"
	- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
- clock-frequency : the input clock frequency for the UART
	 or
  clocks phandle to refer to the clk used as per Documentation/devicetree
  /bindings/clock/clock-bindings.txt

Optional properties:
- current-speed : the current active speed of the UART.
- reg-offset : offset to apply to the mapbase from the start of the registers.
- reg-shift : quantity to shift the register offsets by.
- reg-io-width : the size (in bytes) of the IO accesses that should be
  performed on the device.  There are some systems that require 32-bit
  accesses to the UART (e.g. TI davinci).
- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
  RTAS and should not be registered.
- no-loopback-test: set to indicate that the port does not implements loopback
  test mode
- fifo-size: the fifo size of the UART.
- auto-flow-control: one way to enable automatic flow control support. The
  driver is allowed to detect support for the capability even without this
  property.
- tx-threshold: Specify the TX FIFO low water indication for parts with
  programmable TX FIFO thresholds.
- resets : phandle + reset specifier pairs
- overrun-throttle-ms : how long to pause uart rx when input overrun is encountered.
- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
  line respectively. It will use specified GPIO instead of the peripheral
  function pin for the UART feature. If unsure, don't specify this property.
- aspeed,sirq-polarity-sense: Only applicable to aspeed,ast2500-vuart.
  phandle to aspeed,ast2500-scu compatible syscon alongside register offset
  and bit number to identify how the SIRQ polarity should be configured.
  One possible data source is the LPC/eSPI mode bit.
  Example: aspeed,sirq-polarity-sense = <&syscon 0x70 25>

Note:
* fsl,ns16550:
  ------------
  Freescale DUART is very similar to the PC16552D (and to a
  pair of NS16550A), albeit with some nonstandard behavior such as
  erratum A-004737 (relating to incorrect BRK handling).

  Represents a single port that is compatible with the DUART found
  on many Freescale chips (examples include mpc8349, mpc8548,
  mpc8641d, p4080 and ls2085a).

Example:

	uart@80230000 {
		compatible = "ns8250";
		reg = <0x80230000 0x100>;
		clock-frequency = <3686400>;
		interrupts = <10>;
		reg-shift = <2>;
	};

Example for OMAP UART using GPIO-based modem control signals:

	uart4: serial@49042000 {
		compatible = "ti,omap3-uart";
		reg = <0x49042000 0x400>;
		interrupts = <80>;
		ti,hwmods = "uart4";
		clock-frequency = <48000000>;
		cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
		rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
		dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
		dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
		dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	};