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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Device Tree for Bluestone (APM821xx) board. * * Copyright (c) 2010, Applied Micro Circuits Corporation * Author: Tirumala R Marri <tmarri@apm.com> */ /dts-v1/; / { #address-cells = <2>; #size-cells = <1>; model = "apm,bluestone"; compatible = "apm,bluestone"; dcr-parent = <&{/cpus/cpu@0}>; aliases { ethernet0 = &EMAC0; serial0 = &UART0; serial1 = &UART1; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; model = "PowerPC,apm821xx"; reg = <0x00000000>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; next-level-cache = <&L2C0>; }; }; memory { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ }; UIC0: interrupt-controller0 { compatible = "ibm,uic"; interrupt-controller; cell-index = <0>; dcr-reg = <0x0c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; }; UIC1: interrupt-controller1 { compatible = "ibm,uic"; interrupt-controller; cell-index = <1>; dcr-reg = <0x0d0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; UIC2: interrupt-controller2 { compatible = "ibm,uic"; interrupt-controller; cell-index = <2>; dcr-reg = <0x0e0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; UIC3: interrupt-controller3 { compatible = "ibm,uic"; interrupt-controller; cell-index = <3>; dcr-reg = <0x0f0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ interrupt-parent = <&UIC0>; }; OCM: ocm@400040000 { compatible = "ibm,ocm"; status = "okay"; cell-index = <1>; /* configured in U-Boot */ reg = <4 0x00040000 0x8000>; /* 32K */ }; SDR0: sdr { compatible = "ibm,sdr-apm821xx"; dcr-reg = <0x00e 0x002>; }; CPR0: cpr { compatible = "ibm,cpr-apm821xx"; dcr-reg = <0x00c 0x002>; }; L2C0: l2c { compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache"; dcr-reg = <0x020 0x008 0x030 0x008>; cache-line-size = <32>; cache-size = <262144>; interrupt-parent = <&UIC1>; interrupts = <11 1>; }; plb { compatible = "ibm,plb4"; #address-cells = <2>; #size-cells = <1>; ranges; clock-frequency = <0>; /* Filled in by U-Boot */ SDRAM0: sdram { compatible = "ibm,sdram-apm821xx"; dcr-reg = <0x010 0x002>; }; MAL0: mcmal { compatible = "ibm,mcmal2"; descriptor-memory = "ocm"; dcr-reg = <0x180 0x062>; num-tx-chans = <1>; num-rx-chans = <1>; #address-cells = <0>; #size-cells = <0>; interrupt-parent = <&UIC2>; interrupts = < /*TXEOB*/ 0x6 0x4 /*RXEOB*/ 0x7 0x4 /*SERR*/ 0x3 0x4 /*TXDE*/ 0x4 0x4 /*RXDE*/ 0x5 0x4>; }; POB0: opb { compatible = "ibm,opb"; #address-cells = <1>; #size-cells = <1>; ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; clock-frequency = <0>; /* Filled in by U-Boot */ EBC0: ebc { compatible = "ibm,ebc"; dcr-reg = <0x012 0x002>; #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by U-Boot */ /* ranges property is supplied by U-Boot */ ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>; interrupts = <0x6 0x4>; interrupt-parent = <&UIC1>; nor_flash@0,0 { compatible = "amd,s29gl512n", "cfi-flash"; bank-width = <2>; reg = <0x00000000 0x00000000 0x00400000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "kernel"; reg = <0x00000000 0x00180000>; }; partition@180000 { label = "env"; reg = <0x00180000 0x00020000>; }; partition@1a0000 { label = "u-boot"; reg = <0x001a0000 0x00060000>; }; }; ndfc@1,0 { compatible = "ibm,ndfc"; reg = <0x00000003 0x00000000 0x00002000>; ccr = <0x00001000>; bank-settings = <0x80002222>; #address-cells = <1>; #size-cells = <1>; /* 2Gb Nand Flash */ nand { #address-cells = <1>; #size-cells = <1>; partition@0 { label = "firmware"; reg = <0x00000000 0x00C00000>; }; partition@c00000 { label = "environment"; reg = <0x00C00000 0x00B00000>; }; partition@1700000 { label = "kernel"; reg = <0x01700000 0x00E00000>; }; partition@2500000 { label = "root"; reg = <0x02500000 0x08200000>; }; partition@a700000 { label = "device-tree"; reg = <0x0A700000 0x00B00000>; }; partition@b200000 { label = "config"; reg = <0x0B200000 0x00D00000>; }; partition@bf00000 { label = "diag"; reg = <0x0BF00000 0x00C00000>; }; partition@cb00000 { label = "vendor"; reg = <0x0CB00000 0x3500000>; }; }; }; }; UART0: serial@ef600300 { device_type = "serial"; compatible = "ns16550"; reg = <0xef600300 0x00000008>; virtual-reg = <0xef600300>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC1>; interrupts = <0x1 0x4>; }; UART1: serial@ef600400 { device_type = "serial"; compatible = "ns16550"; reg = <0xef600400 0x00000008>; virtual-reg = <0xef600400>; clock-frequency = <0>; /* Filled in by U-Boot */ current-speed = <0>; /* Filled in by U-Boot */ interrupt-parent = <&UIC0>; interrupts = <0x1 0x4>; }; IIC0: i2c@ef600700 { compatible = "ibm,iic"; reg = <0xef600700 0x00000014>; interrupt-parent = <&UIC0>; interrupts = <0x2 0x4>; #address-cells = <1>; #size-cells = <0>; rtc@68 { compatible = "st,m41t80"; reg = <0x68>; interrupt-parent = <&UIC0>; interrupts = <0x9 0x8>; }; sttm@4C { compatible = "adm,adm1032"; reg = <0x4C>; interrupt-parent = <&UIC1>; interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */ }; }; IIC1: i2c@ef600800 { compatible = "ibm,iic"; reg = <0xef600800 0x00000014>; interrupt-parent = <&UIC0>; interrupts = <0x3 0x4>; }; RGMII0: emac-rgmii@ef601500 { compatible = "ibm,rgmii"; reg = <0xef601500 0x00000008>; has-mdio; }; TAH0: emac-tah@ef601350 { compatible = "ibm,tah"; reg = <0xef601350 0x00000030>; }; EMAC0: ethernet@ef600c00 { device_type = "network"; compatible = "ibm,emac-apm821xx", "ibm,emac4sync"; interrupt-parent = <&EMAC0>; interrupts = <0x0 0x1>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 /*Wake*/ 0x1 &UIC2 0x14 0x4>; reg = <0xef600c00 0x000000c4>; local-mac-address = [000000000000]; /* Filled in by U-Boot */ mal-device = <&MAL0>; mal-tx-channel = <0>; mal-rx-channel = <0>; cell-index = <0>; max-frame-size = <9000>; rx-fifo-size = <16384>; tx-fifo-size = <2048>; phy-mode = "rgmii"; phy-map = <0x00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; tah-device = <&TAH0>; tah-channel = <0>; has-inverted-stacr-oc; has-new-stacr-staopc; }; }; PCIE0: pciex@d00000000 { device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex"; primary; port = <0x0>; /* port number */ reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ 0x0000000c 0x08010000 0x00001000>; /* Registers */ dcr-reg = <0x100 0x020>; sdr-base = <0x300>; /* Outbound ranges, one memory and one IO, * later cannot be changed */ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; /* This drives busses 40 to 0x7f */ bus-range = <0x40 0x7f>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). * We are de-swizzling here because the numbers are actually for * port of the root complex virtual P2P bridge. But I want * to avoid putting a node for it in the tree, so the numbers * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; }; MSI: ppc4xx-msi@C10000000 { compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; reg = < 0xC 0x10000000 0x100 0xC 0x10000000 0x100>; sdr-base = <0x36C>; msi-data = <0x00004440>; msi-mask = <0x0000ffe0>; interrupts =<0 1 2 3 4 5 6 7>; interrupt-parent = <&MSI>; #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; msi-available-ranges = <0x0 0x100>; interrupt-map = < 0 &UIC3 0x18 1 1 &UIC3 0x19 1 2 &UIC3 0x1A 1 3 &UIC3 0x1B 1 4 &UIC3 0x1C 1 5 &UIC3 0x1D 1 6 &UIC3 0x1E 1 7 &UIC3 0x1F 1 >; }; }; }; |