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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 | /* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/media/omap3-isp.h> #include "omap3.dtsi" / { aliases { serial3 = &uart4; }; cpus { /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ cpu: cpu@0 { operating-points = < /* kHz uV */ 300000 1012500 600000 1200000 800000 1325000 >; clock-latency = <300000>; /* From legacy driver */ }; }; ocp@68000000 { uart4: serial@49042000 { compatible = "ti,omap3-uart"; reg = <0x49042000 0x400>; interrupts = <80>; dmas = <&sdma 81 &sdma 82>; dma-names = "tx", "rx"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; abb_mpu_iva: regulator-abb-mpu { compatible = "ti,abb-v1"; regulator-name = "abb_mpu_iva"; #address-cells = <0>; #size-cells = <0>; reg = <0x483072f0 0x8>, <0x48306818 0x4>; reg-names = "base-address", "int-address"; ti,tranxdone-status-mask = <0x4000000>; clocks = <&sys_ck>; ti,settling-time = <30>; ti,clock-cycles = <8>; ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1012500 0 0 0 0 0 1200000 0 0 0 0 0 1325000 0 0 0 0 0 1375000 1 0 0 0 0 >; }; omap3_pmx_core2: pinmux@480025a0 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x480025a0 0x5c>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0xff1f>; }; isp: isp@480bc000 { compatible = "ti,omap3-isp"; reg = <0x480bc000 0x12fc 0x480bd800 0x0600>; interrupts = <24>; iommus = <&mmu_isp>; syscon = <&scm_conf 0x2f0>; ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; #clock-cells = <1>; ports { #address-cells = <1>; #size-cells = <0>; }; }; bandgap: bandgap@48002524 { reg = <0x48002524 0x4>; compatible = "ti,omap36xx-bandgap"; #thermal-sensor-cells = <0>; }; target-module@480cb000 { compatible = "ti,sysc-omap3630-sr", "ti,sysc"; ti,hwmods = "smartreflex_core"; reg = <0x480cb038 0x4>; reg-names = "sysc"; ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; clocks = <&sr2_fck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x480cb000 0x001000>; smartreflex_core: smartreflex@0 { compatible = "ti,omap3-smartreflex-core"; reg = <0 0x400>; interrupts = <19>; }; }; target-module@480c9000 { compatible = "ti,sysc-omap3630-sr", "ti,sysc"; ti,hwmods = "smartreflex_mpu_iva"; reg = <0x480c9038 0x4>; reg-names = "sysc"; ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; clocks = <&sr1_fck>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x480c9000 0x001000>; smartreflex_mpu_iva: smartreflex@480c9000 { compatible = "ti,omap3-smartreflex-mpu-iva"; reg = <0 0x400>; interrupts = <18>; }; }; /* * Note that the sysconfig register layout is a subset of the * "ti,sysc-omap4" type register with just sidle and midle bits * available while omap34xx has "ti,sysc-omap2" type sysconfig. */ sgx_module: target-module@50000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5000fe00 0x4>, <0x5000fe10 0x4>; reg-names = "rev", "sysc"; ti,sysc-midle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>; clocks = <&sgx_fck>, <&sgx_ick>; clock-names = "fck", "ick"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x50000000 0x2000000>; /* * Closed source PowerVR driver, no child device * binding or driver in mainline */ }; }; thermal_zones: thermal-zones { #include "omap3-cpu-thermal.dtsi" }; }; /* OMAP3630 needs dss_96m_fck for VENC */ &venc { clocks = <&dss_tv_fck>, <&dss_96m_fck>; clock-names = "fck", "tv_dac_clk"; }; &ssi { status = "ok"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, <&ssi_ick>; clock-names = "ssi_ssr_fck", "ssi_sst_fck", "ssi_ick"; }; /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-clocks.dtsi" |