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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 | /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */ #ifndef __QCOM_CLK_RCG_H__ #define __QCOM_CLK_RCG_H__ #include <linux/clk-provider.h> #include "clk-regmap.h" #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } struct freq_tbl { unsigned long freq; u8 src; u8 pre_div; u16 m; u16 n; }; /** * struct mn - M/N:D counter * @mnctr_en_bit: bit to enable mn counter * @mnctr_reset_bit: bit to assert mn counter reset * @mnctr_mode_shift: lowest bit of mn counter mode field * @n_val_shift: lowest bit of n value field * @m_val_shift: lowest bit of m value field * @width: number of bits in m/n/d values * @reset_in_cc: true if the mnctr_reset_bit is in the CC register */ struct mn { u8 mnctr_en_bit; u8 mnctr_reset_bit; u8 mnctr_mode_shift; #define MNCTR_MODE_DUAL 0x2 #define MNCTR_MODE_MASK 0x3 u8 n_val_shift; u8 m_val_shift; u8 width; bool reset_in_cc; }; /** * struct pre_div - pre-divider * @pre_div_shift: lowest bit of pre divider field * @pre_div_width: number of bits in predivider */ struct pre_div { u8 pre_div_shift; u8 pre_div_width; }; /** * struct src_sel - source selector * @src_sel_shift: lowest bit of source selection field * @parent_map: map from software's parent index to hardware's src_sel field */ struct src_sel { u8 src_sel_shift; #define SRC_SEL_MASK 0x7 const struct parent_map *parent_map; }; /** * struct clk_rcg - root clock generator * * @ns_reg: NS register * @md_reg: MD register * @mn: mn counter * @p: pre divider * @s: source selector * @freq_tbl: frequency table * @clkr: regmap clock handle * @lock: register lock */ struct clk_rcg { u32 ns_reg; u32 md_reg; struct mn mn; struct pre_div p; struct src_sel s; const struct freq_tbl *freq_tbl; struct clk_regmap clkr; }; extern const struct clk_ops clk_rcg_ops; extern const struct clk_ops clk_rcg_bypass_ops; extern const struct clk_ops clk_rcg_bypass2_ops; extern const struct clk_ops clk_rcg_pixel_ops; extern const struct clk_ops clk_rcg_esc_ops; extern const struct clk_ops clk_rcg_lcc_ops; #define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) /** * struct clk_dyn_rcg - root clock generator with glitch free mux * * @mux_sel_bit: bit to switch glitch free mux * @ns_reg: NS0 and NS1 register * @md_reg: MD0 and MD1 register * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux * @mn: mn counter (banked) * @s: source selector (banked) * @freq_tbl: frequency table * @clkr: regmap clock handle * @lock: register lock */ struct clk_dyn_rcg { u32 ns_reg[2]; u32 md_reg[2]; u32 bank_reg; u8 mux_sel_bit; struct mn mn[2]; struct pre_div p[2]; struct src_sel s[2]; const struct freq_tbl *freq_tbl; struct clk_regmap clkr; }; extern const struct clk_ops clk_dyn_rcg_ops; #define to_clk_dyn_rcg(_hw) \ container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr) /** * struct clk_rcg2 - root clock generator * * @cmd_rcgr: corresponds to *_CMD_RCGR * @mnd_width: number of bits in m/n/d values * @hid_width: number of bits in half integer divider * @safe_src_index: safe src index value * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table * @clkr: regmap clock handle * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG */ struct clk_rcg2 { u32 cmd_rcgr; u8 mnd_width; u8 hid_width; u8 safe_src_index; const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; struct clk_regmap clkr; u8 cfg_off; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) extern const struct clk_ops clk_rcg2_ops; extern const struct clk_ops clk_rcg2_floor_ops; extern const struct clk_ops clk_edp_pixel_ops; extern const struct clk_ops clk_byte_ops; extern const struct clk_ops clk_byte2_ops; extern const struct clk_ops clk_pixel_ops; extern const struct clk_ops clk_gfx3d_ops; extern const struct clk_ops clk_rcg2_shared_ops; struct clk_rcg_dfs_data { struct clk_rcg2 *rcg; struct clk_init_data *init; }; #define DEFINE_RCG_DFS(r) \ { .rcg = &r##_src, .init = &r##_init } extern int qcom_cc_register_rcg_dfs(struct regmap *regmap, const struct clk_rcg_dfs_data *rcgs, size_t len); #endif |