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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 | * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX Required properties: - compatible : Should be one of "fsl,imx25-sdma" "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" "fsl,imx51-sdma" "fsl,imx53-sdma" "fsl,imx6q-sdma" "fsl,imx7d-sdma" "fsl,imx8mq-sdma" The -to variants should be preferred since they allow to determine the correct ROM script addresses needed for the driver to work without additional firmware. - reg : Should contain SDMA registers location and length - interrupts : Should contain SDMA interrupt - #dma-cells : Must be <3>. The first cell specifies the DMA request/event ID. See details below about the second and third cell. - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM scripts firmware The second cell of dma phandle specifies the peripheral type of DMA transfer. The full ID of peripheral types can be found below. ID transfer type --------------------- 0 MCU domain SSI 1 Shared SSI 2 MMC 3 SDHC 4 MCU domain UART 5 Shared UART 6 FIRI 7 MCU domain CSPI 8 Shared CSPI 9 SIM 10 ATA 11 CCM 12 External peripheral 13 Memory Stick Host Controller 14 Shared Memory Stick Host Controller 15 DSP 16 Memory 17 FIFO type Memory 18 SPDIF 19 IPU Memory 20 ASRC 21 ESAI 22 SSI Dual FIFO (needs firmware ver >= 2) 23 Shared ASRC 24 SAI The third cell specifies the transfer priority as below. ID transfer priority ------------------------- 0 High 1 Medium 2 Low Optional properties: - gpr : The phandle to the General Purpose Register (GPR) node. - fsl,sdma-event-remap : Register bits of sdma event remap, the format is <reg shift val>. reg is the GPR register offset. shift is the bit position inside the GPR register. val is the value of the bit (0 or 1). Examples: sdma@83fb0000 { compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; #dma-cells = <3>; fsl,sdma-ram-script-name = "sdma-imx51.bin"; }; DMA clients connected to the i.MX SDMA controller must use the format described in the dma.txt file. Examples: ssi2: ssi@70014000 { compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; clocks = <&clks 49>; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; }; Using the fsl,sdma-event-remap property: If we want to use SDMA on the SAI1 port on a MX6SX: &sdma { gpr = <&gpr>; /* SDMA events remap for SAI1_RX and SAI1_TX */ fsl,sdma-event-remap = <0 15 1>, <0 16 1>; }; The fsl,sdma-event-remap property in this case has two values: - <0 15 1> means that the offset is 0, so GPR0 is the register of the SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. Setting bit 15 to 1 selects SAI1_RX. - <0 16 1> means that the offset is 0, so GPR0 is the register of the SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. Setting bit 16 to 1 selects SAI1_TX. |