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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 | /* * Device Tree Source for IBM Embedded PPC 476 Platform * * Copyright © 2011 Tony Breeds IBM Corporation * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without * any warranty of any kind, whether express or implied. */ /dts-v1/; /memreserve/ 0x01f00000 0x00100000; // spin table / { #address-cells = <2>; #size-cells = <2>; model = "ibm,currituck"; compatible = "ibm,currituck"; dcr-parent = <&{/cpus/cpu@0}>; aliases { serial0 = &UART0; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; model = "PowerPC,476"; reg = <0>; clock-frequency = <1600000000>; // 1.6 GHz timebase-frequency = <100000000>; // 100Mhz i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; status = "okay"; }; cpu@1 { device_type = "cpu"; model = "PowerPC,476"; reg = <1>; clock-frequency = <1600000000>; // 1.6 GHz timebase-frequency = <100000000>; // 100Mhz i-cache-line-size = <32>; d-cache-line-size = <32>; i-cache-size = <32768>; d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; status = "disabled"; enable-method = "spin-table"; cpu-release-addr = <0x0 0x01f00000>; }; }; memory { device_type = "memory"; reg = <0x0 0x0 0x0 0x0>; // filled in by zImage }; MPIC: interrupt-controller { compatible = "chrp,open-pic"; interrupt-controller; dcr-reg = <0xffc00000 0x00040000>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; }; plb { compatible = "ibm,plb6"; #address-cells = <2>; #size-cells = <2>; ranges; clock-frequency = <200000000>; // 200Mhz POB0: opb { compatible = "ibm,opb-4xx", "ibm,opb"; #address-cells = <1>; #size-cells = <1>; /* Wish there was a nicer way of specifying a full * 32-bit range */ ranges = <0x00000000 0x00000200 0x00000000 0x80000000 0x80000000 0x00000200 0x80000000 0x80000000>; clock-frequency = <100000000>; UART0: serial@10000000 { device_type = "serial"; compatible = "ns16750", "ns16550"; reg = <0x10000000 0x00000008>; virtual-reg = <0xe1000000>; clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART] current-speed = <115200>; interrupt-parent = <&MPIC>; interrupts = <34 2>; }; FPGA0: fpga@50000000 { compatible = "ibm,currituck-fpga"; reg = <0x50000000 0x4>; }; IIC0: i2c@0 { compatible = "ibm,iic-currituck", "ibm,iic"; reg = <0x0 0x00000014>; interrupt-parent = <&MPIC>; interrupts = <79 2>; #address-cells = <1>; #size-cells = <0>; rtc@68 { compatible = "st,m41t80", "m41st85"; reg = <0x68>; }; }; }; PCIE0: pciex@10100000000 { // 4xGBIF1 device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; primary; port = <0x0>; /* port number */ reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */ 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ dcr-reg = <0x80 0x20>; // pci_space < pci_addr > < cpu_addr > < size > ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>; /* Inbound starting at 0 to memsize filled in by zImage */ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>; /* This drives busses 0 to 0xf */ bus-range = <0x0 0xf>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). * We are de-swizzling here because the numbers are actually for * port of the root complex virtual P2P bridge. But I want * to avoid putting a node for it in the tree, so the numbers * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */ 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */ 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */ 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>; }; PCIE1: pciex@30100000000 { // 4xGBIF0 device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; primary; port = <0x1>; /* port number */ reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */ 0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ dcr-reg = <0x60 0x20>; ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000 0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>; /* Inbound starting at 0 to memsize filled in by zImage */ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>; /* This drives busses 0 to 0xf */ bus-range = <0x0 0xf>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). * We are de-swizzling here because the numbers are actually for * port of the root complex virtual P2P bridge. But I want * to avoid putting a node for it in the tree, so the numbers * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */ 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */ 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */ 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>; }; PCIE2: pciex@38100000000 { // 2xGBIF0 device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex"; primary; port = <0x2>; /* port number */ reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */ 0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */ dcr-reg = <0xA0 0x20>; ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000 0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>; /* Inbound starting at 0 to memsize filled in by zImage */ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>; /* This drives busses 0 to 0xf */ bus-range = <0x0 0xf>; /* Legacy interrupts (note the weird polarity, the bridge seems * to invert PCIe legacy interrupts). * We are de-swizzling here because the numbers are actually for * port of the root complex virtual P2P bridge. But I want * to avoid putting a node for it in the tree, so the numbers * below are basically de-swizzled numbers. * The real slot is on idsel 0, so the swizzling is 1:1 */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = < 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */ 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */ 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */ 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>; }; }; chosen { stdout-path = &UART0; }; }; |