# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX8ULP IOMUX Controller

maintainers:
  - Jacky Bai <ping.bai@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imx8ulp-iomuxc1

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 5 integers and represents the mux and config
          setting for one pin. The first 4 integers <mux_config_reg input_reg
          mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_config_reg" indicates the offset of mux register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_mode" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    iomuxc: pinctrl@298c0000 {
        compatible = "fsl,imx8ulp-iomuxc1";
        reg = <0x298c0000 0x10000>;

        pinctrl_lpuart5: lpuart5grp {
            fsl,pins =
                <0x0138 0x08F0 0x4 0x3	0x3>,
                <0x013C 0x08EC 0x4 0x3	0x3>;
        };
    };

...