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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 | /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2014 MediaTek Inc. * Author: James Liao <jamesjj.liao@mediatek.com> */ #ifndef __DRV_CLK_MTK_H #define __DRV_CLK_MTK_H #include <linux/regmap.h> #include <linux/bitops.h> #include <linux/clk-provider.h> #include <linux/platform_device.h> struct clk; struct clk_onecell_data; #define MAX_MUX_GATE_BIT 31 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) #define MHZ (1000 * 1000) struct mtk_fixed_clk { int id; const char *name; const char *parent; unsigned long rate; }; #define FIXED_CLK(_id, _name, _parent, _rate) { \ .id = _id, \ .name = _name, \ .parent = _parent, \ .rate = _rate, \ } void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, struct clk_onecell_data *clk_data); struct mtk_fixed_factor { int id; const char *name; const char *parent_name; int mult; int div; }; #define FACTOR(_id, _name, _parent, _mult, _div) { \ .id = _id, \ .name = _name, \ .parent_name = _parent, \ .mult = _mult, \ .div = _div, \ } void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, struct clk_onecell_data *clk_data); struct mtk_composite { int id; const char *name; const char * const *parent_names; const char *parent; unsigned flags; uint32_t mux_reg; uint32_t divider_reg; uint32_t gate_reg; signed char mux_shift; signed char mux_width; signed char gate_shift; signed char divider_shift; signed char divider_width; u8 mux_flags; signed char num_parents; }; #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ _width, _gate, _flags, _muxflags) { \ .id = _id, \ .name = _name, \ .mux_reg = _reg, \ .mux_shift = _shift, \ .mux_width = _width, \ .gate_reg = _reg, \ .gate_shift = _gate, \ .divider_shift = -1, \ .parent_names = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .flags = _flags, \ .mux_flags = _muxflags, \ } /* * In case the rate change propagation to parent clocks is undesirable, * this macro allows to specify the clock flags manually. */ #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ _gate, _flags) \ MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ _shift, _width, _gate, _flags, 0) /* * Unless necessary, all MUX_GATE clocks propagate rate changes to their * parent clock by default. */ #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ _gate, CLK_SET_RATE_PARENT) #define MUX(_id, _name, _parents, _reg, _shift, _width) \ MUX_FLAGS(_id, _name, _parents, _reg, \ _shift, _width, CLK_SET_RATE_PARENT) #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ .id = _id, \ .name = _name, \ .mux_reg = _reg, \ .mux_shift = _shift, \ .mux_width = _width, \ .gate_shift = -1, \ .divider_shift = -1, \ .parent_names = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .flags = _flags, \ } #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ _div_width, _div_shift) { \ .id = _id, \ .parent = _parent, \ .name = _name, \ .divider_reg = _div_reg, \ .divider_shift = _div_shift, \ .divider_width = _div_width, \ .gate_reg = _gate_reg, \ .gate_shift = _gate_shift, \ .mux_shift = -1, \ .flags = 0, \ } struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock); void mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; u32 set_ofs; }; struct mtk_gate { int id; const char *name; const char *parent_name; const struct mtk_gate_regs *regs; int shift; const struct clk_ops *ops; unsigned long flags; }; int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, int num, struct clk_onecell_data *clk_data); int mtk_clk_register_gates_with_dev(struct device_node *node, const struct mtk_gate *clks, int num, struct clk_onecell_data *clk_data, struct device *dev); struct mtk_clk_divider { int id; const char *name; const char *parent_name; unsigned long flags; u32 div_reg; unsigned char div_shift; unsigned char div_width; unsigned char clk_divider_flags; const struct clk_div_table *clk_div_table; }; #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ .id = _id, \ .name = _name, \ .parent_name = _parent, \ .div_reg = _reg, \ .div_shift = _shift, \ .div_width = _width, \ } void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); void mtk_free_clk_data(struct clk_onecell_data *clk_data); #define HAVE_RST_BAR BIT(0) #define PLL_AO BIT(1) struct mtk_pll_div_table { u32 div; unsigned long freq; }; struct mtk_pll_data { int id; const char *name; u32 reg; u32 pwr_reg; u32 en_mask; u32 pd_reg; u32 tuner_reg; u32 tuner_en_reg; u8 tuner_en_bit; int pd_shift; unsigned int flags; const struct clk_ops *ops; u32 rst_bar_mask; unsigned long fmin; unsigned long fmax; int pcwbits; int pcwibits; u32 pcw_reg; int pcw_shift; u32 pcw_chg_reg; const struct mtk_pll_div_table *div_table; const char *parent_name; u32 en_reg; u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ }; void mtk_clk_register_plls(struct device_node *node, const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); void mtk_register_reset_controller(struct device_node *np, unsigned int num_regs, int regofs); void mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs); struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; }; int mtk_clk_simple_probe(struct platform_device *pdev); #endif /* __DRV_CLK_MTK_H */ |