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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 | // SPDX-License-Identifier: GPL-2.0-only /* * drivers/clk/clk-axm5516.c * * Provides clock implementations for three different types of clock devices on * the Axxia device: PLL clock, a clock divider and a clock mux. * * Copyright (C) 2014 LSI Corporation */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <dt-bindings/clock/lsi,axm5516-clks.h> /** * struct axxia_clk - Common struct to all Axxia clocks. * @hw: clk_hw for the common clk framework * @regmap: Regmap for the clock control registers */ struct axxia_clk { struct clk_hw hw; struct regmap *regmap; }; #define to_axxia_clk(_hw) container_of(_hw, struct axxia_clk, hw) /** * struct axxia_pllclk - Axxia PLL generated clock. * @aclk: Common struct * @reg: Offset into regmap for PLL control register */ struct axxia_pllclk { struct axxia_clk aclk; u32 reg; }; #define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk) /** * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the * parent clock rate. */ static unsigned long axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate) { struct axxia_clk *aclk = to_axxia_clk(hw); struct axxia_pllclk *pll = to_axxia_pllclk(aclk); unsigned long rate, fbdiv, refdiv, postdiv; u32 control; regmap_read(aclk->regmap, pll->reg, &control); postdiv = ((control >> 0) & 0xf) + 1; fbdiv = ((control >> 4) & 0xfff) + 3; refdiv = ((control >> 16) & 0x1f) + 1; rate = (parent_rate / (refdiv * postdiv)) * fbdiv; return rate; } static const struct clk_ops axxia_pllclk_ops = { .recalc_rate = axxia_pllclk_recalc, }; /** * struct axxia_divclk - Axxia clock divider * @aclk: Common struct * @reg: Offset into regmap for PLL control register * @shift: Bit position for divider value * @width: Number of bits in divider value */ struct axxia_divclk { struct axxia_clk aclk; u32 reg; u32 shift; u32 width; }; #define to_axxia_divclk(_aclk) container_of(_aclk, struct axxia_divclk, aclk) /** * axxia_divclk_recalc_rate - Calculate clock divider output rage */ static unsigned long axxia_divclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct axxia_clk *aclk = to_axxia_clk(hw); struct axxia_divclk *divclk = to_axxia_divclk(aclk); u32 ctrl, div; regmap_read(aclk->regmap, divclk->reg, &ctrl); div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1)); return parent_rate / div; } static const struct clk_ops axxia_divclk_ops = { .recalc_rate = axxia_divclk_recalc_rate, }; /** * struct axxia_clkmux - Axxia clock mux * @aclk: Common struct * @reg: Offset into regmap for PLL control register * @shift: Bit position for selection value * @width: Number of bits in selection value */ struct axxia_clkmux { struct axxia_clk aclk; u32 reg; u32 shift; u32 width; }; #define to_axxia_clkmux(_aclk) container_of(_aclk, struct axxia_clkmux, aclk) /** * axxia_clkmux_get_parent - Return the index of selected parent clock */ static u8 axxia_clkmux_get_parent(struct clk_hw *hw) { struct axxia_clk *aclk = to_axxia_clk(hw); struct axxia_clkmux *mux = to_axxia_clkmux(aclk); u32 ctrl, parent; regmap_read(aclk->regmap, mux->reg, &ctrl); parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1); return (u8) parent; } static const struct clk_ops axxia_clkmux_ops = { .get_parent = axxia_clkmux_get_parent, }; /* * PLLs */ static struct axxia_pllclk clk_fab_pll = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_fab_pll", .parent_names = (const char *[]){ "clk_ref0" }, .num_parents = 1, .ops = &axxia_pllclk_ops, }, .reg = 0x01800, }; static struct axxia_pllclk clk_cpu_pll = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu_pll", .parent_names = (const char *[]){ "clk_ref0" }, .num_parents = 1, .ops = &axxia_pllclk_ops, }, .reg = 0x02000, }; static struct axxia_pllclk clk_sys_pll = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_sys_pll", .parent_names = (const char *[]){ "clk_ref0" }, .num_parents = 1, .ops = &axxia_pllclk_ops, }, .reg = 0x02800, }; static struct axxia_pllclk clk_sm0_pll = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_sm0_pll", .parent_names = (const char *[]){ "clk_ref2" }, .num_parents = 1, .ops = &axxia_pllclk_ops, }, .reg = 0x03000, }; static struct axxia_pllclk clk_sm1_pll = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_sm1_pll", .parent_names = (const char *[]){ "clk_ref1" }, .num_parents = 1, .ops = &axxia_pllclk_ops, }, .reg = 0x03800, }; /* * Clock dividers */ static struct axxia_divclk clk_cpu0_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu0_div", .parent_names = (const char *[]){ "clk_cpu_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x10008, .shift = 0, .width = 4, }; static struct axxia_divclk clk_cpu1_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu1_div", .parent_names = (const char *[]){ "clk_cpu_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x10008, .shift = 4, .width = 4, }; static struct axxia_divclk clk_cpu2_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu2_div", .parent_names = (const char *[]){ "clk_cpu_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x10008, .shift = 8, .width = 4, }; static struct axxia_divclk clk_cpu3_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu3_div", .parent_names = (const char *[]){ "clk_cpu_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x10008, .shift = 12, .width = 4, }; static struct axxia_divclk clk_nrcp_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_nrcp_div", .parent_names = (const char *[]){ "clk_sys_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x1000c, .shift = 0, .width = 4, }; static struct axxia_divclk clk_sys_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_sys_div", .parent_names = (const char *[]){ "clk_sys_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x1000c, .shift = 4, .width = 4, }; static struct axxia_divclk clk_fab_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_fab_div", .parent_names = (const char *[]){ "clk_fab_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x1000c, .shift = 8, .width = 4, }; static struct axxia_divclk clk_per_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_per_div", .parent_names = (const char *[]){ "clk_sm1_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x1000c, .shift = 12, .width = 4, }; static struct axxia_divclk clk_mmc_div = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_mmc_div", .parent_names = (const char *[]){ "clk_sm1_pll" }, .num_parents = 1, .ops = &axxia_divclk_ops, }, .reg = 0x1000c, .shift = 16, .width = 4, }; /* * Clock MUXes */ static struct axxia_clkmux clk_cpu0_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu0", .parent_names = (const char *[]){ "clk_ref0", "clk_cpu_pll", "clk_cpu0_div", "clk_cpu0_div" }, .num_parents = 4, .ops = &axxia_clkmux_ops, }, .reg = 0x10000, .shift = 0, .width = 2, }; static struct axxia_clkmux clk_cpu1_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu1", .parent_names = (const char *[]){ "clk_ref0", "clk_cpu_pll", "clk_cpu1_div", "clk_cpu1_div" }, .num_parents = 4, .ops = &axxia_clkmux_ops, }, .reg = 0x10000, .shift = 2, .width = 2, }; static struct axxia_clkmux clk_cpu2_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu2", .parent_names = (const char *[]){ "clk_ref0", "clk_cpu_pll", "clk_cpu2_div", "clk_cpu2_div" }, .num_parents = 4, .ops = &axxia_clkmux_ops, }, .reg = 0x10000, .shift = 4, .width = 2, }; static struct axxia_clkmux clk_cpu3_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_cpu3", .parent_names = (const char *[]){ "clk_ref0", "clk_cpu_pll", "clk_cpu3_div", "clk_cpu3_div" }, .num_parents = 4, .ops = &axxia_clkmux_ops, }, .reg = 0x10000, .shift = 6, .width = 2, }; static struct axxia_clkmux clk_nrcp_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_nrcp", .parent_names = (const char *[]){ "clk_ref0", "clk_sys_pll", "clk_nrcp_div", "clk_nrcp_div" }, .num_parents = 4, .ops = &axxia_clkmux_ops, }, .reg = 0x10004, .shift = 0, .width = 2, }; static struct axxia_clkmux clk_sys_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_sys", .parent_names = (const char *[]){ "clk_ref0", "clk_sys_pll", "clk_sys_div", "clk_sys_div" }, .num_parents = 4, .ops = &axxia_clkmux_ops, }, .reg = 0x10004, .shift = 2, .width = 2, }; static struct axxia_clkmux clk_fab_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_fab", .parent_names = (const char *[]){ "clk_ref0", "clk_fab_pll", "clk_fab_div", "clk_fab_div" }, .num_parents = 4, .ops = &axxia_clkmux_ops, }, .reg = 0x10004, .shift = 4, .width = 2, }; static struct axxia_clkmux clk_per_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_per", .parent_names = (const char *[]){ "clk_ref1", "clk_per_div" }, .num_parents = 2, .ops = &axxia_clkmux_ops, }, .reg = 0x10004, .shift = 6, .width = 1, }; static struct axxia_clkmux clk_mmc_mux = { .aclk.hw.init = &(struct clk_init_data){ .name = "clk_mmc", .parent_names = (const char *[]){ "clk_ref1", "clk_mmc_div" }, .num_parents = 2, .ops = &axxia_clkmux_ops, }, .reg = 0x10004, .shift = 9, .width = 1, }; /* Table of all supported clocks indexed by the clock identifiers from the * device tree binding */ static struct axxia_clk *axmclk_clocks[] = { [AXXIA_CLK_FAB_PLL] = &clk_fab_pll.aclk, [AXXIA_CLK_CPU_PLL] = &clk_cpu_pll.aclk, [AXXIA_CLK_SYS_PLL] = &clk_sys_pll.aclk, [AXXIA_CLK_SM0_PLL] = &clk_sm0_pll.aclk, [AXXIA_CLK_SM1_PLL] = &clk_sm1_pll.aclk, [AXXIA_CLK_FAB_DIV] = &clk_fab_div.aclk, [AXXIA_CLK_SYS_DIV] = &clk_sys_div.aclk, [AXXIA_CLK_NRCP_DIV] = &clk_nrcp_div.aclk, [AXXIA_CLK_CPU0_DIV] = &clk_cpu0_div.aclk, [AXXIA_CLK_CPU1_DIV] = &clk_cpu1_div.aclk, [AXXIA_CLK_CPU2_DIV] = &clk_cpu2_div.aclk, [AXXIA_CLK_CPU3_DIV] = &clk_cpu3_div.aclk, [AXXIA_CLK_PER_DIV] = &clk_per_div.aclk, [AXXIA_CLK_MMC_DIV] = &clk_mmc_div.aclk, [AXXIA_CLK_FAB] = &clk_fab_mux.aclk, [AXXIA_CLK_SYS] = &clk_sys_mux.aclk, [AXXIA_CLK_NRCP] = &clk_nrcp_mux.aclk, [AXXIA_CLK_CPU0] = &clk_cpu0_mux.aclk, [AXXIA_CLK_CPU1] = &clk_cpu1_mux.aclk, [AXXIA_CLK_CPU2] = &clk_cpu2_mux.aclk, [AXXIA_CLK_CPU3] = &clk_cpu3_mux.aclk, [AXXIA_CLK_PER] = &clk_per_mux.aclk, [AXXIA_CLK_MMC] = &clk_mmc_mux.aclk, }; static struct clk_hw * of_clk_axmclk_get(struct of_phandle_args *clkspec, void *unused) { unsigned int idx = clkspec->args[0]; if (idx >= ARRAY_SIZE(axmclk_clocks)) { pr_err("%s: invalid index %u\n", __func__, idx); return ERR_PTR(-EINVAL); } return &axmclk_clocks[idx]->hw; } static const struct regmap_config axmclk_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x1fffc, .fast_io = true, }; static const struct of_device_id axmclk_match_table[] = { { .compatible = "lsi,axm5516-clks" }, { } }; MODULE_DEVICE_TABLE(of, axmclk_match_table); static int axmclk_probe(struct platform_device *pdev) { void __iomem *base; struct resource *res; int i, ret; struct device *dev = &pdev->dev; struct regmap *regmap; size_t num_clks; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) return PTR_ERR(base); regmap = devm_regmap_init_mmio(dev, base, &axmclk_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); num_clks = ARRAY_SIZE(axmclk_clocks); pr_info("axmclk: supporting %zu clocks\n", num_clks); /* Update each entry with the allocated regmap and register the clock * with the common clock framework */ for (i = 0; i < num_clks; i++) { axmclk_clocks[i]->regmap = regmap; ret = devm_clk_hw_register(dev, &axmclk_clocks[i]->hw); if (ret) return ret; } return of_clk_add_hw_provider(dev->of_node, of_clk_axmclk_get, NULL); } static int axmclk_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); return 0; } static struct platform_driver axmclk_driver = { .probe = axmclk_probe, .remove = axmclk_remove, .driver = { .name = "clk-axm5516", .of_match_table = axmclk_match_table, }, }; static int __init axmclk_init(void) { return platform_driver_register(&axmclk_driver); } core_initcall(axmclk_init); static void __exit axmclk_exit(void) { platform_driver_unregister(&axmclk_driver); } module_exit(axmclk_exit); MODULE_DESCRIPTION("AXM5516 clock driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:clk-axm5516"); |