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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 | /* * Copyright 2012 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * */ /* * Authors: Dave Airlie <airlied@redhat.com> */ #ifndef __AST_DRV_H__ #define __AST_DRV_H__ #include <linux/i2c.h> #include <linux/i2c-algo-bit.h> #include <linux/io.h> #include <linux/types.h> #include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include <drm/drm_encoder.h> #include <drm/drm_mode.h> #include <drm/drm_framebuffer.h> #include <drm/drm_fb_helper.h> #define DRIVER_AUTHOR "Dave Airlie" #define DRIVER_NAME "ast" #define DRIVER_DESC "AST" #define DRIVER_DATE "20120228" #define DRIVER_MAJOR 0 #define DRIVER_MINOR 1 #define DRIVER_PATCHLEVEL 0 #define PCI_CHIP_AST2000 0x2000 #define PCI_CHIP_AST2100 0x2010 enum ast_chip { AST2000, AST2100, AST1100, AST2200, AST2150, AST2300, AST2400, AST2500, AST2600, }; enum ast_tx_chip { AST_TX_NONE, AST_TX_SIL164, AST_TX_ITE66121, AST_TX_DP501, }; #define AST_DRAM_512Mx16 0 #define AST_DRAM_1Gx16 1 #define AST_DRAM_512Mx32 2 #define AST_DRAM_1Gx32 3 #define AST_DRAM_2Gx16 6 #define AST_DRAM_4Gx16 7 #define AST_DRAM_8Gx16 8 /* * Cursor plane */ #define AST_MAX_HWC_WIDTH 64 #define AST_MAX_HWC_HEIGHT 64 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2) #define AST_HWC_SIGNATURE_SIZE 32 #define AST_DEFAULT_HWC_NUM 2 /* define for signature structure */ #define AST_HWC_SIGNATURE_CHECKSUM 0x00 #define AST_HWC_SIGNATURE_SizeX 0x04 #define AST_HWC_SIGNATURE_SizeY 0x08 #define AST_HWC_SIGNATURE_X 0x0C #define AST_HWC_SIGNATURE_Y 0x10 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18 struct ast_cursor_plane { struct drm_plane base; struct { struct drm_gem_vram_object *gbo; struct dma_buf_map map; u64 off; } hwc[AST_DEFAULT_HWC_NUM]; unsigned int next_hwc_index; }; static inline struct ast_cursor_plane * to_ast_cursor_plane(struct drm_plane *plane) { return container_of(plane, struct ast_cursor_plane, base); } /* * Connector with i2c channel */ struct ast_i2c_chan { struct i2c_adapter adapter; struct drm_device *dev; struct i2c_algo_bit_data bit; }; struct ast_connector { struct drm_connector base; struct ast_i2c_chan *i2c; }; static inline struct ast_connector * to_ast_connector(struct drm_connector *connector) { return container_of(connector, struct ast_connector, base); } /* * Device */ struct ast_private { struct drm_device base; void __iomem *regs; void __iomem *ioregs; void __iomem *dp501_fw_buf; enum ast_chip chip; bool vga2_clone; uint32_t dram_bus_width; uint32_t dram_type; uint32_t mclk; int fb_mtrr; struct drm_plane primary_plane; struct ast_cursor_plane cursor_plane; struct drm_crtc crtc; struct drm_encoder encoder; struct ast_connector connector; bool support_wide_screen; enum { ast_use_p2a, ast_use_dt, ast_use_defaults } config_mode; enum ast_tx_chip tx_chip_type; u8 dp501_maxclk; u8 *dp501_fw_addr; const struct firmware *dp501_fw; /* dp501 fw */ }; static inline struct ast_private *to_ast_private(struct drm_device *dev) { return container_of(dev, struct ast_private, base); } struct ast_private *ast_device_create(const struct drm_driver *drv, struct pci_dev *pdev, unsigned long flags); #define AST_IO_AR_PORT_WRITE (0x40) #define AST_IO_MISC_PORT_WRITE (0x42) #define AST_IO_VGA_ENABLE_PORT (0x43) #define AST_IO_SEQ_PORT (0x44) #define AST_IO_DAC_INDEX_READ (0x47) #define AST_IO_DAC_INDEX_WRITE (0x48) #define AST_IO_DAC_DATA (0x49) #define AST_IO_GR_PORT (0x4E) #define AST_IO_CRTC_PORT (0x54) #define AST_IO_INPUT_STATUS1_READ (0x5A) #define AST_IO_MISC_PORT_READ (0x4C) #define AST_IO_MM_OFFSET (0x380) #define AST_IO_VGAIR1_VREFRESH BIT(3) #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ #define __ast_read(x) \ static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ u##x val = 0;\ val = ioread##x(ast->regs + reg); \ return val;\ } __ast_read(8); __ast_read(16); __ast_read(32) #define __ast_io_read(x) \ static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ u##x val = 0;\ val = ioread##x(ast->ioregs + reg); \ return val;\ } __ast_io_read(8); __ast_io_read(16); __ast_io_read(32); #define __ast_write(x) \ static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ iowrite##x(val, ast->regs + reg);\ } __ast_write(8); __ast_write(16); __ast_write(32); #define __ast_io_write(x) \ static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ iowrite##x(val, ast->ioregs + reg);\ } __ast_io_write(8); __ast_io_write(16); #undef __ast_io_write static inline void ast_set_index_reg(struct ast_private *ast, uint32_t base, uint8_t index, uint8_t val) { ast_io_write16(ast, base, ((u16)val << 8) | index); } void ast_set_index_reg_mask(struct ast_private *ast, uint32_t base, uint8_t index, uint8_t mask, uint8_t val); uint8_t ast_get_index_reg(struct ast_private *ast, uint32_t base, uint8_t index); uint8_t ast_get_index_reg_mask(struct ast_private *ast, uint32_t base, uint8_t index, uint8_t mask); static inline void ast_open_key(struct ast_private *ast) { ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); } #define AST_VIDMEM_SIZE_8M 0x00800000 #define AST_VIDMEM_SIZE_16M 0x01000000 #define AST_VIDMEM_SIZE_32M 0x02000000 #define AST_VIDMEM_SIZE_64M 0x04000000 #define AST_VIDMEM_SIZE_128M 0x08000000 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M struct ast_vbios_stdtable { u8 misc; u8 seq[4]; u8 crtc[25]; u8 ar[20]; u8 gr[9]; }; struct ast_vbios_enhtable { u32 ht; u32 hde; u32 hfp; u32 hsync; u32 vt; u32 vde; u32 vfp; u32 vsync; u32 dclk_index; u32 flags; u32 refresh_rate; u32 refresh_rate_index; u32 mode_id; }; struct ast_vbios_dclk_info { u8 param1; u8 param2; u8 param3; }; struct ast_vbios_mode_info { const struct ast_vbios_stdtable *std_table; const struct ast_vbios_enhtable *enh_table; }; struct ast_crtc_state { struct drm_crtc_state base; /* Last known format of primary plane */ const struct drm_format_info *format; struct ast_vbios_mode_info vbios_mode_info; }; #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base) int ast_mode_config_init(struct ast_private *ast); #define AST_MM_ALIGN_SHIFT 4 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1) #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4) #define AST_DP501_FW_VERSION_1 BIT(4) #define AST_DP501_PNP_CONNECTED BIT(1) #define AST_DP501_DEFAULT_DCLK 65 #define AST_DP501_GBL_VERSION 0xf000 #define AST_DP501_PNPMONITOR 0xf010 #define AST_DP501_LINKRATE 0xf014 #define AST_DP501_EDID_DATA 0xf020 /* Define for Soc scratched reg */ #define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6) //#define AST_VRAM_INIT_BY_BMC BIT(7) //#define AST_VRAM_INIT_READY BIT(6) int ast_mm_init(struct ast_private *ast); /* ast post */ void ast_enable_vga(struct drm_device *dev); void ast_enable_mmio(struct drm_device *dev); bool ast_is_vga_enabled(struct drm_device *dev); void ast_post_gpu(struct drm_device *dev); u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); void ast_patch_ahb_2500(struct ast_private *ast); /* ast dp501 */ void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata); u8 ast_get_dp501_max_clk(struct drm_device *dev); void ast_init_3rdtx(struct drm_device *dev); #endif |