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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 | // SPDX-License-Identifier: GPL-2.0+ /* * Driver for NEC VR4100 series General-purpose I/O Unit. * * Copyright (C) 2002 MontaVista Software Inc. * Author: Yoichi Yuasa <source@mvista.com> * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org> */ #include <linux/errno.h> #include <linux/fs.h> #include <linux/gpio/driver.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/spinlock.h> #include <linux/types.h> #include <asm/vr41xx/giu.h> #include <asm/vr41xx/irq.h> #include <asm/vr41xx/vr41xx.h> MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>"); MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver"); MODULE_LICENSE("GPL"); #define GIUIOSELL 0x00 #define GIUIOSELH 0x02 #define GIUPIODL 0x04 #define GIUPIODH 0x06 #define GIUINTSTATL 0x08 #define GIUINTSTATH 0x0a #define GIUINTENL 0x0c #define GIUINTENH 0x0e #define GIUINTTYPL 0x10 #define GIUINTTYPH 0x12 #define GIUINTALSELL 0x14 #define GIUINTALSELH 0x16 #define GIUINTHTSELL 0x18 #define GIUINTHTSELH 0x1a #define GIUPODATL 0x1c #define GIUPODATEN 0x1c #define GIUPODATH 0x1e #define PIOEN0 0x0100 #define PIOEN1 0x0200 #define GIUPODAT 0x1e #define GIUFEDGEINHL 0x20 #define GIUFEDGEINHH 0x22 #define GIUREDGEINHL 0x24 #define GIUREDGEINHH 0x26 #define GIUUSEUPDN 0x1e0 #define GIUTERMUPDN 0x1e2 #define GPIO_HAS_PULLUPDOWN_IO 0x0001 #define GPIO_HAS_OUTPUT_ENABLE 0x0002 #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100 enum { GPIO_INPUT, GPIO_OUTPUT, }; static DEFINE_SPINLOCK(giu_lock); static unsigned long giu_flags; static void __iomem *giu_base; static struct gpio_chip vr41xx_gpio_chip; #define giu_read(offset) readw(giu_base + (offset)) #define giu_write(offset, value) writew((value), giu_base + (offset)) #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE) #define GIUINT_HIGH_OFFSET 16 #define GIUINT_HIGH_MAX 32 static inline u16 giu_set(u16 offset, u16 set) { u16 data; data = giu_read(offset); data |= set; giu_write(offset, data); return data; } static inline u16 giu_clear(u16 offset, u16 clear) { u16 data; data = giu_read(offset); data &= ~clear; giu_write(offset, data); return data; } static void ack_giuint_low(struct irq_data *d) { giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq)); } static void mask_giuint_low(struct irq_data *d) { giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq)); } static void mask_ack_giuint_low(struct irq_data *d) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(d->irq); giu_clear(GIUINTENL, 1 << pin); giu_write(GIUINTSTATL, 1 << pin); } static void unmask_giuint_low(struct irq_data *d) { giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq)); } static unsigned int startup_giuint(struct irq_data *data) { int ret; ret = gpiochip_lock_as_irq(&vr41xx_gpio_chip, irqd_to_hwirq(data)); if (ret) { dev_err(vr41xx_gpio_chip.parent, "unable to lock HW IRQ %lu for IRQ\n", data->hwirq); return ret; } /* Satisfy the .enable semantics by unmasking the line */ unmask_giuint_low(data); return 0; } static void shutdown_giuint(struct irq_data *data) { mask_giuint_low(data); gpiochip_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq); } static struct irq_chip giuint_low_irq_chip = { .name = "GIUINTL", .irq_ack = ack_giuint_low, .irq_mask = mask_giuint_low, .irq_mask_ack = mask_ack_giuint_low, .irq_unmask = unmask_giuint_low, .irq_startup = startup_giuint, .irq_shutdown = shutdown_giuint, }; static void ack_giuint_high(struct irq_data *d) { giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); } static void mask_giuint_high(struct irq_data *d) { giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); } static void mask_ack_giuint_high(struct irq_data *d) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET; giu_clear(GIUINTENH, 1 << pin); giu_write(GIUINTSTATH, 1 << pin); } static void unmask_giuint_high(struct irq_data *d) { giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); } static struct irq_chip giuint_high_irq_chip = { .name = "GIUINTH", .irq_ack = ack_giuint_high, .irq_mask = mask_giuint_high, .irq_mask_ack = mask_ack_giuint_high, .irq_unmask = unmask_giuint_high, }; static int giu_get_irq(unsigned int irq) { u16 pendl, pendh, maskl, maskh; int i; pendl = giu_read(GIUINTSTATL); pendh = giu_read(GIUINTSTATH); maskl = giu_read(GIUINTENL); maskh = giu_read(GIUINTENH); maskl &= pendl; maskh &= pendh; if (maskl) { for (i = 0; i < 16; i++) { if (maskl & (1 << i)) return GIU_IRQ(i); } } else if (maskh) { for (i = 0; i < 16; i++) { if (maskh & (1 << i)) return GIU_IRQ(i + GIUINT_HIGH_OFFSET); } } printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n", maskl, pendl, maskh, pendh); atomic_inc(&irq_err_count); return -EINVAL; } void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal) { u16 mask; if (pin < GIUINT_HIGH_OFFSET) { mask = 1 << pin; if (trigger != IRQ_TRIGGER_LEVEL) { giu_set(GIUINTTYPL, mask); if (signal == IRQ_SIGNAL_HOLD) giu_set(GIUINTHTSELL, mask); else giu_clear(GIUINTHTSELL, mask); if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) { switch (trigger) { case IRQ_TRIGGER_EDGE_FALLING: giu_set(GIUFEDGEINHL, mask); giu_clear(GIUREDGEINHL, mask); break; case IRQ_TRIGGER_EDGE_RISING: giu_clear(GIUFEDGEINHL, mask); giu_set(GIUREDGEINHL, mask); break; default: giu_set(GIUFEDGEINHL, mask); giu_set(GIUREDGEINHL, mask); break; } } irq_set_chip_and_handler(GIU_IRQ(pin), &giuint_low_irq_chip, handle_edge_irq); } else { giu_clear(GIUINTTYPL, mask); giu_clear(GIUINTHTSELL, mask); irq_set_chip_and_handler(GIU_IRQ(pin), &giuint_low_irq_chip, handle_level_irq); } giu_write(GIUINTSTATL, mask); } else if (pin < GIUINT_HIGH_MAX) { mask = 1 << (pin - GIUINT_HIGH_OFFSET); if (trigger != IRQ_TRIGGER_LEVEL) { giu_set(GIUINTTYPH, mask); if (signal == IRQ_SIGNAL_HOLD) giu_set(GIUINTHTSELH, mask); else giu_clear(GIUINTHTSELH, mask); if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) { switch (trigger) { case IRQ_TRIGGER_EDGE_FALLING: giu_set(GIUFEDGEINHH, mask); giu_clear(GIUREDGEINHH, mask); break; case IRQ_TRIGGER_EDGE_RISING: giu_clear(GIUFEDGEINHH, mask); giu_set(GIUREDGEINHH, mask); break; default: giu_set(GIUFEDGEINHH, mask); giu_set(GIUREDGEINHH, mask); break; } } irq_set_chip_and_handler(GIU_IRQ(pin), &giuint_high_irq_chip, handle_edge_irq); } else { giu_clear(GIUINTTYPH, mask); giu_clear(GIUINTHTSELH, mask); irq_set_chip_and_handler(GIU_IRQ(pin), &giuint_high_irq_chip, handle_level_irq); } giu_write(GIUINTSTATH, mask); } } EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger); void vr41xx_set_irq_level(unsigned int pin, irq_level_t level) { u16 mask; if (pin < GIUINT_HIGH_OFFSET) { mask = 1 << pin; if (level == IRQ_LEVEL_HIGH) giu_set(GIUINTALSELL, mask); else giu_clear(GIUINTALSELL, mask); giu_write(GIUINTSTATL, mask); } else if (pin < GIUINT_HIGH_MAX) { mask = 1 << (pin - GIUINT_HIGH_OFFSET); if (level == IRQ_LEVEL_HIGH) giu_set(GIUINTALSELH, mask); else giu_clear(GIUINTALSELH, mask); giu_write(GIUINTSTATH, mask); } } EXPORT_SYMBOL_GPL(vr41xx_set_irq_level); static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir) { u16 offset, mask, reg; unsigned long flags; if (pin >= chip->ngpio) return -EINVAL; if (pin < 16) { offset = GIUIOSELL; mask = 1 << pin; } else if (pin < 32) { offset = GIUIOSELH; mask = 1 << (pin - 16); } else { if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) { offset = GIUPODATEN; mask = 1 << (pin - 32); } else { switch (pin) { case 48: offset = GIUPODATH; mask = PIOEN0; break; case 49: offset = GIUPODATH; mask = PIOEN1; break; default: return -EINVAL; } } } spin_lock_irqsave(&giu_lock, flags); reg = giu_read(offset); if (dir == GPIO_OUTPUT) reg |= mask; else reg &= ~mask; giu_write(offset, reg); spin_unlock_irqrestore(&giu_lock, flags); return 0; } static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin) { u16 reg, mask; if (pin >= chip->ngpio) return -EINVAL; if (pin < 16) { reg = giu_read(GIUPIODL); mask = 1 << pin; } else if (pin < 32) { reg = giu_read(GIUPIODH); mask = 1 << (pin - 16); } else if (pin < 48) { reg = giu_read(GIUPODATL); mask = 1 << (pin - 32); } else { reg = giu_read(GIUPODATH); mask = 1 << (pin - 48); } if (reg & mask) return 1; return 0; } static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin, int value) { u16 offset, mask, reg; unsigned long flags; if (pin >= chip->ngpio) return; if (pin < 16) { offset = GIUPIODL; mask = 1 << pin; } else if (pin < 32) { offset = GIUPIODH; mask = 1 << (pin - 16); } else if (pin < 48) { offset = GIUPODATL; mask = 1 << (pin - 32); } else { offset = GIUPODATH; mask = 1 << (pin - 48); } spin_lock_irqsave(&giu_lock, flags); reg = giu_read(offset); if (value) reg |= mask; else reg &= ~mask; giu_write(offset, reg); spin_unlock_irqrestore(&giu_lock, flags); } static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { return giu_set_direction(chip, offset, GPIO_INPUT); } static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) { vr41xx_gpio_set(chip, offset, value); return giu_set_direction(chip, offset, GPIO_OUTPUT); } static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { if (offset >= chip->ngpio) return -EINVAL; return GIU_IRQ_BASE + offset; } static struct gpio_chip vr41xx_gpio_chip = { .label = "vr41xx", .owner = THIS_MODULE, .direction_input = vr41xx_gpio_direction_input, .get = vr41xx_gpio_get, .direction_output = vr41xx_gpio_direction_output, .set = vr41xx_gpio_set, .to_irq = vr41xx_gpio_to_irq, }; static int giu_probe(struct platform_device *pdev) { unsigned int trigger, i, pin; struct irq_chip *chip; int irq; switch (pdev->id) { case GPIO_50PINS_PULLUPDOWN: giu_flags = GPIO_HAS_PULLUPDOWN_IO; vr41xx_gpio_chip.ngpio = 50; break; case GPIO_36PINS: vr41xx_gpio_chip.ngpio = 36; break; case GPIO_48PINS_EDGE_SELECT: giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT; vr41xx_gpio_chip.ngpio = 48; break; default: dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id); return -ENODEV; } giu_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(giu_base)) return PTR_ERR(giu_base); vr41xx_gpio_chip.parent = &pdev->dev; if (gpiochip_add_data(&vr41xx_gpio_chip, NULL)) return -ENODEV; giu_write(GIUINTENL, 0); giu_write(GIUINTENH, 0); trigger = giu_read(GIUINTTYPH) << 16; trigger |= giu_read(GIUINTTYPL); for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { pin = GPIO_PIN_OF_IRQ(i); if (pin < GIUINT_HIGH_OFFSET) chip = &giuint_low_irq_chip; else chip = &giuint_high_irq_chip; if (trigger & (1 << pin)) irq_set_chip_and_handler(i, chip, handle_edge_irq); else irq_set_chip_and_handler(i, chip, handle_level_irq); } irq = platform_get_irq(pdev, 0); if (irq < 0 || irq >= nr_irqs) return -EBUSY; return cascade_irq(irq, giu_get_irq); } static int giu_remove(struct platform_device *pdev) { if (giu_base) { giu_base = NULL; } return 0; } static struct platform_driver giu_device_driver = { .probe = giu_probe, .remove = giu_remove, .driver = { .name = "GIU", }, }; module_platform_driver(giu_device_driver); |