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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 | /* * include/asm-xtensa/atomic.h * * Atomic operations that C can't guarantee us. Useful for resource counting.. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2008 Tensilica Inc. */ #ifndef _XTENSA_ATOMIC_H #define _XTENSA_ATOMIC_H #include <linux/stringify.h> #include <linux/types.h> #include <asm/processor.h> #include <asm/cmpxchg.h> #include <asm/barrier.h> /* * This Xtensa implementation assumes that the right mechanism * for exclusion is for locking interrupts to level EXCM_LEVEL. * * Locking interrupts looks like this: * * rsil a15, TOPLEVEL * <code> * wsr a15, PS * rsync * * Note that a15 is used here because the register allocation * done by the compiler is not guaranteed and a window overflow * may not occur between the rsil and wsr instructions. By using * a15 in the rsil, the machine is guaranteed to be in a state * where no register reference will cause an overflow. */ /** * atomic_read - read atomic variable * @v: pointer of type atomic_t * * Atomically reads the value of @v. */ #define atomic_read(v) READ_ONCE((v)->counter) /** * atomic_set - set atomic variable * @v: pointer of type atomic_t * @i: required value * * Atomically sets the value of @v to @i. */ #define atomic_set(v,i) WRITE_ONCE((v)->counter, (i)) #if XCHAL_HAVE_EXCLUSIVE #define ATOMIC_OP(op) \ static inline void atomic_##op(int i, atomic_t *v) \ { \ unsigned long tmp; \ int result; \ \ __asm__ __volatile__( \ "1: l32ex %[tmp], %[addr]\n" \ " " #op " %[result], %[tmp], %[i]\n" \ " s32ex %[result], %[addr]\n" \ " getex %[result]\n" \ " beqz %[result], 1b\n" \ : [result] "=&a" (result), [tmp] "=&a" (tmp) \ : [i] "a" (i), [addr] "a" (v) \ : "memory" \ ); \ } \ #define ATOMIC_OP_RETURN(op) \ static inline int atomic_##op##_return(int i, atomic_t *v) \ { \ unsigned long tmp; \ int result; \ \ __asm__ __volatile__( \ "1: l32ex %[tmp], %[addr]\n" \ " " #op " %[result], %[tmp], %[i]\n" \ " s32ex %[result], %[addr]\n" \ " getex %[result]\n" \ " beqz %[result], 1b\n" \ " " #op " %[result], %[tmp], %[i]\n" \ : [result] "=&a" (result), [tmp] "=&a" (tmp) \ : [i] "a" (i), [addr] "a" (v) \ : "memory" \ ); \ \ return result; \ } #define ATOMIC_FETCH_OP(op) \ static inline int atomic_fetch_##op(int i, atomic_t *v) \ { \ unsigned long tmp; \ int result; \ \ __asm__ __volatile__( \ "1: l32ex %[tmp], %[addr]\n" \ " " #op " %[result], %[tmp], %[i]\n" \ " s32ex %[result], %[addr]\n" \ " getex %[result]\n" \ " beqz %[result], 1b\n" \ : [result] "=&a" (result), [tmp] "=&a" (tmp) \ : [i] "a" (i), [addr] "a" (v) \ : "memory" \ ); \ \ return tmp; \ } #elif XCHAL_HAVE_S32C1I #define ATOMIC_OP(op) \ static inline void atomic_##op(int i, atomic_t * v) \ { \ unsigned long tmp; \ int result; \ \ __asm__ __volatile__( \ "1: l32i %[tmp], %[mem]\n" \ " wsr %[tmp], scompare1\n" \ " " #op " %[result], %[tmp], %[i]\n" \ " s32c1i %[result], %[mem]\n" \ " bne %[result], %[tmp], 1b\n" \ : [result] "=&a" (result), [tmp] "=&a" (tmp), \ [mem] "+m" (*v) \ : [i] "a" (i) \ : "memory" \ ); \ } \ #define ATOMIC_OP_RETURN(op) \ static inline int atomic_##op##_return(int i, atomic_t * v) \ { \ unsigned long tmp; \ int result; \ \ __asm__ __volatile__( \ "1: l32i %[tmp], %[mem]\n" \ " wsr %[tmp], scompare1\n" \ " " #op " %[result], %[tmp], %[i]\n" \ " s32c1i %[result], %[mem]\n" \ " bne %[result], %[tmp], 1b\n" \ " " #op " %[result], %[result], %[i]\n" \ : [result] "=&a" (result), [tmp] "=&a" (tmp), \ [mem] "+m" (*v) \ : [i] "a" (i) \ : "memory" \ ); \ \ return result; \ } #define ATOMIC_FETCH_OP(op) \ static inline int atomic_fetch_##op(int i, atomic_t * v) \ { \ unsigned long tmp; \ int result; \ \ __asm__ __volatile__( \ "1: l32i %[tmp], %[mem]\n" \ " wsr %[tmp], scompare1\n" \ " " #op " %[result], %[tmp], %[i]\n" \ " s32c1i %[result], %[mem]\n" \ " bne %[result], %[tmp], 1b\n" \ : [result] "=&a" (result), [tmp] "=&a" (tmp), \ [mem] "+m" (*v) \ : [i] "a" (i) \ : "memory" \ ); \ \ return result; \ } #else /* XCHAL_HAVE_S32C1I */ #define ATOMIC_OP(op) \ static inline void atomic_##op(int i, atomic_t * v) \ { \ unsigned int vval; \ \ __asm__ __volatile__( \ " rsil a15, "__stringify(TOPLEVEL)"\n" \ " l32i %[result], %[mem]\n" \ " " #op " %[result], %[result], %[i]\n" \ " s32i %[result], %[mem]\n" \ " wsr a15, ps\n" \ " rsync\n" \ : [result] "=&a" (vval), [mem] "+m" (*v) \ : [i] "a" (i) \ : "a15", "memory" \ ); \ } \ #define ATOMIC_OP_RETURN(op) \ static inline int atomic_##op##_return(int i, atomic_t * v) \ { \ unsigned int vval; \ \ __asm__ __volatile__( \ " rsil a15,"__stringify(TOPLEVEL)"\n" \ " l32i %[result], %[mem]\n" \ " " #op " %[result], %[result], %[i]\n" \ " s32i %[result], %[mem]\n" \ " wsr a15, ps\n" \ " rsync\n" \ : [result] "=&a" (vval), [mem] "+m" (*v) \ : [i] "a" (i) \ : "a15", "memory" \ ); \ \ return vval; \ } #define ATOMIC_FETCH_OP(op) \ static inline int atomic_fetch_##op(int i, atomic_t * v) \ { \ unsigned int tmp, vval; \ \ __asm__ __volatile__( \ " rsil a15,"__stringify(TOPLEVEL)"\n" \ " l32i %[result], %[mem]\n" \ " " #op " %[tmp], %[result], %[i]\n" \ " s32i %[tmp], %[mem]\n" \ " wsr a15, ps\n" \ " rsync\n" \ : [result] "=&a" (vval), [tmp] "=&a" (tmp), \ [mem] "+m" (*v) \ : [i] "a" (i) \ : "a15", "memory" \ ); \ \ return vval; \ } #endif /* XCHAL_HAVE_S32C1I */ #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_OPS(add) ATOMIC_OPS(sub) #undef ATOMIC_OPS #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OPS(and) ATOMIC_OPS(or) ATOMIC_OPS(xor) #undef ATOMIC_OPS #undef ATOMIC_FETCH_OP #undef ATOMIC_OP_RETURN #undef ATOMIC_OP #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) #endif /* _XTENSA_ATOMIC_H */ |