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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 | // SPDX-License-Identifier: GPL-2.0+ // // Copyright 2011 Freescale Semiconductor, Inc. // Copyright 2011 Linaro Ltd. #include "imx51-pinfunc.h" #include <dt-bindings/clock/imx5-clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> / { #address-cells = <1>; #size-cells = <1>; /* * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. */ chosen {}; aliases { ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; i2c0 = &i2c1; i2c1 = &i2c2; mmc0 = &esdhc1; mmc1 = &esdhc2; mmc2 = &esdhc3; mmc3 = &esdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &cspi; }; tzic: tz-interrupt-controller@e0000000 { compatible = "fsl,imx51-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; reg = <0xe0000000 0x4000>; }; clocks { ckil { compatible = "fsl,imx-ckil", "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; ckih2 { compatible = "fsl,imx-ckih2", "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; osc { compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a8"; reg = <0>; clock-latency = <62500>; clocks = <&clks IMX5_CLK_CPU_PODF>; clock-names = "cpu"; operating-points = < 166000 1000000 600000 1050000 800000 1100000 >; voltage-tolerance = <5>; }; }; pmu: pmu { compatible = "arm,cortex-a8-pmu"; interrupt-parent = <&tzic>; interrupts = <77>; }; usbphy0: usbphy0 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX5_CLK_USB_PHY_GATE>; clock-names = "main_clk"; #phy-cells = <0>; }; capture-subsystem { compatible = "fsl,imx-capture-subsystem"; ports = <&ipu_csi0>, <&ipu_csi1>; }; display-subsystem { compatible = "fsl,imx-display-subsystem"; ports = <&ipu_di0>, <&ipu_di1>; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; iram: sram@1ffe0000 { compatible = "mmio-sram"; reg = <0x1ffe0000 0x20000>; }; gpu: gpu@30000000 { compatible = "amd,imageon-200.1", "amd,imageon"; reg = <0x30000000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = <12>; interrupt-names = "kgsl_3d0_irq"; clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; clock-names = "core_clk", "mem_iface_clk"; }; ipu: ipu@40000000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ipu"; reg = <0x40000000 0x20000000>; interrupts = <11 10>; clocks = <&clks IMX5_CLK_IPU_GATE>, <&clks IMX5_CLK_IPU_DI0_GATE>, <&clks IMX5_CLK_IPU_DI1_GATE>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; ipu_csi0: port@0 { reg = <0>; }; ipu_csi1: port@1 { reg = <1>; }; ipu_di0: port@2 { reg = <2>; ipu_di0_disp1: endpoint { }; }; ipu_di1: port@3 { reg = <3>; ipu_di1_disp2: endpoint { }; }; }; bus@70000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x70000000 0x10000000>; ranges; spba@70000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x70000000 0x40000>; ranges; esdhc1: mmc@70004000 { compatible = "fsl,imx51-esdhc"; reg = <0x70004000 0x4000>; interrupts = <1>; clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC1_PER_GATE>; clock-names = "ipg", "ahb", "per"; status = "disabled"; }; esdhc2: mmc@70008000 { compatible = "fsl,imx51-esdhc"; reg = <0x70008000 0x4000>; interrupts = <2>; clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC2_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; }; uart3: serial@7000c000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x7000c000 0x4000>; interrupts = <33>; clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; ecspi1: spi@70010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ecspi"; reg = <0x70010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, <&clks IMX5_CLK_ECSPI1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; ssi2: ssi@70014000 { #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, <&clks IMX5_CLK_SSI2_ROOT_GATE>; clock-names = "ipg", "baud"; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; esdhc3: mmc@70020000 { compatible = "fsl,imx51-esdhc"; reg = <0x70020000 0x4000>; interrupts = <3>; clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC3_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; }; esdhc4: mmc@70024000 { compatible = "fsl,imx51-esdhc"; reg = <0x70024000 0x4000>; interrupts = <4>; clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, <&clks IMX5_CLK_DUMMY>, <&clks IMX5_CLK_ESDHC4_PER_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; status = "disabled"; }; }; aipstz1: bridge@73f00000 { compatible = "fsl,imx51-aipstz"; reg = <0x73f00000 0x60>; }; usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; interrupts = <18>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 0>; fsl,usbphy = <&usbphy0>; status = "disabled"; }; usbh1: usb@73f80200 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80200 0x0200>; interrupts = <14>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 1>; dr_mode = "host"; status = "disabled"; }; usbh2: usb@73f80400 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80400 0x0200>; interrupts = <16>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 2>; dr_mode = "host"; status = "disabled"; }; usbh3: usb@73f80600 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80600 0x0200>; interrupts = <17>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; fsl,usbmisc = <&usbmisc 3>; dr_mode = "host"; status = "disabled"; }; usbmisc: usbmisc@73f80800 { #index-cells = <1>; compatible = "fsl,imx51-usbmisc"; reg = <0x73f80800 0x200>; clocks = <&clks IMX5_CLK_USBOH3_GATE>; }; gpio1: gpio@73f84000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f84000 0x4000>; interrupts = <50 51>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@73f88000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f88000 0x4000>; interrupts = <52 53>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@73f8c000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f8c000 0x4000>; interrupts = <54 55>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio4: gpio@73f90000 { compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; reg = <0x73f90000 0x4000>; interrupts = <56 57>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; kpp: kpp@73f94000 { compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; reg = <0x73f94000 0x4000>; interrupts = <60>; clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; wdog1: wdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; clocks = <&clks IMX5_CLK_DUMMY>; }; wdog2: wdog@73f9c000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f9c000 0x4000>; interrupts = <59>; clocks = <&clks IMX5_CLK_DUMMY>; status = "disabled"; }; gpt: timer@73fa0000 { compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; reg = <0x73fa0000 0x4000>; interrupts = <39>; clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, <&clks IMX5_CLK_GPT_HF_GATE>; clock-names = "ipg", "per"; }; iomuxc: iomuxc@73fa8000 { compatible = "fsl,imx51-iomuxc"; reg = <0x73fa8000 0x4000>; }; pwm1: pwm@73fb4000 { #pwm-cells = <3>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, <&clks IMX5_CLK_PWM1_HF_GATE>; clock-names = "ipg", "per"; interrupts = <61>; }; pwm2: pwm@73fb8000 { #pwm-cells = <3>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, <&clks IMX5_CLK_PWM2_HF_GATE>; clock-names = "ipg", "per"; interrupts = <94>; }; uart1: serial@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; interrupts = <31>; clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; uart2: serial@73fc0000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fc0000 0x4000>; interrupts = <32>; clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; src: reset-controller@73fd0000 { compatible = "fsl,imx51-src"; reg = <0x73fd0000 0x4000>; interrupts = <75>; #reset-cells = <1>; }; clks: ccm@73fd4000{ compatible = "fsl,imx51-ccm"; reg = <0x73fd4000 0x4000>; interrupts = <0 71 0x04 0 72 0x04>; #clock-cells = <1>; }; }; bus@80000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x80000000 0x10000000>; ranges; aipstz2: bridge@83f00000 { compatible = "fsl,imx51-aipstz"; reg = <0x83f00000 0x60>; }; iim: efuse@83f98000 { compatible = "fsl,imx51-iim", "fsl,imx27-iim"; reg = <0x83f98000 0x4000>; interrupts = <69>; clocks = <&clks IMX5_CLK_IIM_GATE>; }; tigerp: tigerp@83fa0000 { compatible = "fsl,imx51-tigerp"; reg = <0x83fa0000 0x28>; }; owire: owire@83fa4000 { compatible = "fsl,imx51-owire", "fsl,imx21-owire"; reg = <0x83fa4000 0x4000>; interrupts = <88>; clocks = <&clks IMX5_CLK_OWIRE_GATE>; status = "disabled"; }; ecspi2: spi@83fac000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-ecspi"; reg = <0x83fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, <&clks IMX5_CLK_ECSPI2_PER_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; sdma: dma-controller@83fb0000 { compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; reg = <0x83fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; }; cspi: spi@83fc0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; reg = <0x83fc0000 0x4000>; interrupts = <38>; clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, <&clks IMX5_CLK_CSPI_IPG_GATE>; clock-names = "ipg", "per"; status = "disabled"; }; i2c2: i2c@83fc4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; reg = <0x83fc4000 0x4000>; interrupts = <63>; clocks = <&clks IMX5_CLK_I2C2_GATE>; status = "disabled"; }; i2c1: i2c@83fc8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; reg = <0x83fc8000 0x4000>; interrupts = <62>; clocks = <&clks IMX5_CLK_I2C1_GATE>; status = "disabled"; }; ssi1: ssi@83fcc000 { #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, <&clks IMX5_CLK_SSI1_ROOT_GATE>; clock-names = "ipg", "baud"; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; audmux: audmux@83fd0000 { compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; reg = <0x83fd0000 0x4000>; clocks = <&clks IMX5_CLK_DUMMY>; clock-names = "audmux"; status = "disabled"; }; m4if: m4if@83fd8000 { compatible = "fsl,imx51-m4if"; reg = <0x83fd8000 0x1000>; }; weim: weim@83fda000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,imx51-weim"; reg = <0x83fda000 0x1000>; clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; ranges = < 0 0 0xb0000000 0x08000000 1 0 0xb8000000 0x08000000 2 0 0xc0000000 0x08000000 3 0 0xc8000000 0x04000000 4 0 0xcc000000 0x02000000 5 0 0xce000000 0x02000000 >; status = "disabled"; }; nfc: nand@83fdb000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx51-nand"; reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; interrupts = <8>; clocks = <&clks IMX5_CLK_NFC_GATE>; status = "disabled"; }; pata: pata@83fe0000 { compatible = "fsl,imx51-pata", "fsl,imx27-pata"; reg = <0x83fe0000 0x4000>; interrupts = <70>; clocks = <&clks IMX5_CLK_PATA_GATE>; status = "disabled"; }; ssi3: ssi@83fe8000 { #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, <&clks IMX5_CLK_SSI3_ROOT_GATE>; clock-names = "ipg", "baud"; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; fec: ethernet@83fec000 { compatible = "fsl,imx51-fec", "fsl,imx27-fec"; reg = <0x83fec000 0x4000>; interrupts = <87>; clocks = <&clks IMX5_CLK_FEC_GATE>, <&clks IMX5_CLK_FEC_GATE>, <&clks IMX5_CLK_FEC_GATE>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; vpu: vpu@83ff4000 { compatible = "fsl,imx51-vpu", "cnm,codahx4"; reg = <0x83ff4000 0x1000>; interrupts = <9>; clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, <&clks IMX5_CLK_VPU_GATE>; clock-names = "per", "ahb"; resets = <&src 1>; iram = <&iram>; }; sahara: crypto@83ff8000 { compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; reg = <0x83ff8000 0x4000>; interrupts = <19 20>; clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, <&clks IMX5_CLK_SAHARA_IPG_GATE>; clock-names = "ipg", "ahb"; }; }; }; }; |