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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 | // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> * * Gated clock implementation */ #include <linux/clk-provider.h> #include <linux/export.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/io.h> #include <linux/err.h> #include <linux/string.h> #include "clk.h" /** * DOC: basic gateable clock which can gate and ungate its output * * Traits of this clock: * prepare - clk_(un)prepare only ensures parent is (un)prepared * enable - clk_enable and clk_disable are functional & control gating * rate - inherits rate from parent. No clk_set_rate support * parent - fixed parent. No clk_set_parent support */ struct clk_gate2 { struct clk_hw hw; void __iomem *reg; u8 bit_idx; u8 cgr_val; u8 flags; spinlock_t *lock; unsigned int *share_count; }; #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) static int clk_gate2_enable(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); u32 reg; unsigned long flags; int ret = 0; spin_lock_irqsave(gate->lock, flags); if (gate->share_count && (*gate->share_count)++ > 0) goto out; if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) { ret = clk_gate_ops.enable(hw); } else { reg = readl(gate->reg); reg &= ~(3 << gate->bit_idx); reg |= gate->cgr_val << gate->bit_idx; writel(reg, gate->reg); } out: spin_unlock_irqrestore(gate->lock, flags); return ret; } static void clk_gate2_disable(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); u32 reg; unsigned long flags; spin_lock_irqsave(gate->lock, flags); if (gate->share_count) { if (WARN_ON(*gate->share_count == 0)) goto out; else if (--(*gate->share_count) > 0) goto out; } if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) { clk_gate_ops.disable(hw); } else { reg = readl(gate->reg); reg &= ~(3 << gate->bit_idx); writel(reg, gate->reg); } out: spin_unlock_irqrestore(gate->lock, flags); } static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) { u32 val = readl(reg); if (((val >> bit_idx) & 1) == 1) return 1; return 0; } static int clk_gate2_is_enabled(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) return clk_gate_ops.is_enabled(hw); return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); } static void clk_gate2_disable_unused(struct clk_hw *hw) { struct clk_gate2 *gate = to_clk_gate2(hw); unsigned long flags; u32 reg; if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) return; spin_lock_irqsave(gate->lock, flags); if (!gate->share_count || *gate->share_count == 0) { reg = readl(gate->reg); reg &= ~(3 << gate->bit_idx); writel(reg, gate->reg); } spin_unlock_irqrestore(gate->lock, flags); } static const struct clk_ops clk_gate2_ops = { .enable = clk_gate2_enable, .disable = clk_gate2_disable, .disable_unused = clk_gate2_disable_unused, .is_enabled = clk_gate2_is_enabled, }; struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 clk_gate2_flags, spinlock_t *lock, unsigned int *share_count) { struct clk_gate2 *gate; struct clk_hw *hw; struct clk_init_data init; int ret; gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL); if (!gate) return ERR_PTR(-ENOMEM); /* struct clk_gate2 assignments */ gate->reg = reg; gate->bit_idx = bit_idx; gate->cgr_val = cgr_val; gate->flags = clk_gate2_flags; gate->lock = lock; gate->share_count = share_count; init.name = name; init.ops = &clk_gate2_ops; init.flags = flags; init.parent_names = parent_name ? &parent_name : NULL; init.num_parents = parent_name ? 1 : 0; gate->hw.init = &init; hw = &gate->hw; ret = clk_hw_register(dev, hw); if (ret) { kfree(gate); return ERR_PTR(ret); } return hw; } EXPORT_SYMBOL_GPL(clk_hw_register_gate2); |