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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 | /* * dtsi file for Broadcom (BRCM) Vulcan processor * * Copyright (c) 2013-2016 Broadcom * Author: Zi Shen Lim <zlim@broadcom.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include <dt-bindings/interrupt-controller/arm-gic.h> / { model = "Broadcom Vulcan"; compatible = "brcm,vulcan-soc"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; /* just 4 cpus now, 128 needed in full config */ cpus { #address-cells = <0x2>; #size-cells = <0x0>; cpu@0 { device_type = "cpu"; compatible = "brcm,vulcan", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu@1 { device_type = "cpu"; compatible = "brcm,vulcan", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu@2 { device_type = "cpu"; compatible = "brcm,vulcan", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu@3 { device_type = "cpu"; compatible = "brcm,vulcan", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; gic: interrupt-controller@400080000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-controller; #redistributor-regions = <1>; reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ <0x04 0x01000000 0x0 0x1000000>; /* GICR */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; gicits: gic-its@40010000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; }; pmu { compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ }; clk125mhz: uart_clk125mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; clock-output-names = "clk125mhz"; }; pci { compatible = "pci-host-ecam-generic"; device_type = "pci"; #interrupt-cells = <1>; #address-cells = <3>; #size-cells = <2>; /* ECAM at 0x3000_0000 - 0x4000_0000 */ reg = <0x0 0x30000000 0x0 0x10000000>; reg-names = "PCI ECAM"; /* * PCI ranges: * IO no supported * MEM 0x4000_0000 - 0x6000_0000 * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 */ ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; interrupt-map-mask = <0 0 0 7>; interrupt-map = /* addr pin ic icaddr icintr */ <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; msi-parent = <&gicits>; dma-coherent; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; uart0: serial@402020000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x04 0x02020000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk125mhz>; clock-names = "apb_pclk"; }; }; }; |