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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 | /* * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2012 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/slab.h> #include <linux/err.h> #include "clk.h" /** * struct clk_pfd - IMX PFD clock * @clk_hw: clock source * @reg: PFD register address * @idx: the index of PFD encoded in the register * * PFD clock found on i.MX6 series. Each register for PFD has 4 clk_pfd * data encoded, and member idx is used to specify the one. And each * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc. */ struct clk_pfd { struct clk_hw hw; void __iomem *reg; u8 idx; }; #define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw) #define SET 0x4 #define CLR 0x8 #define OTG 0xc static int clk_pfd_enable(struct clk_hw *hw) { struct clk_pfd *pfd = to_clk_pfd(hw); writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); return 0; } static void clk_pfd_disable(struct clk_hw *hw) { struct clk_pfd *pfd = to_clk_pfd(hw); writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); } static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pfd *pfd = to_clk_pfd(hw); u64 tmp = parent_rate; u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; tmp *= 18; do_div(tmp, frac); return tmp; } static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { u64 tmp = *prate; u8 frac; tmp = tmp * 18 + rate / 2; do_div(tmp, rate); frac = tmp; if (frac < 12) frac = 12; else if (frac > 35) frac = 35; tmp = *prate; tmp *= 18; do_div(tmp, frac); return tmp; } static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_pfd *pfd = to_clk_pfd(hw); u64 tmp = parent_rate; u8 frac; tmp = tmp * 18 + rate / 2; do_div(tmp, rate); frac = tmp; if (frac < 12) frac = 12; else if (frac > 35) frac = 35; writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); return 0; } static int clk_pfd_is_enabled(struct clk_hw *hw) { struct clk_pfd *pfd = to_clk_pfd(hw); if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1))) return 0; return 1; } static const struct clk_ops clk_pfd_ops = { .enable = clk_pfd_enable, .disable = clk_pfd_disable, .recalc_rate = clk_pfd_recalc_rate, .round_rate = clk_pfd_round_rate, .set_rate = clk_pfd_set_rate, .is_enabled = clk_pfd_is_enabled, }; struct clk *imx_clk_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx) { struct clk_pfd *pfd; struct clk *clk; struct clk_init_data init; pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); if (!pfd) return ERR_PTR(-ENOMEM); pfd->reg = reg; pfd->idx = idx; init.name = name; init.ops = &clk_pfd_ops; init.flags = 0; init.parent_names = &parent_name; init.num_parents = 1; pfd->hw.init = &init; clk = clk_register(NULL, &pfd->hw); if (IS_ERR(clk)) kfree(pfd); return clk; } |