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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * * Copyright (C) 2012 Marvell * * Lior Amsalem <alior@marvell.com> * Gregory CLEMENT <gregory.clement@free-electrons.com> * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> * Ben Dooks <ben.dooks@codethink.co.uk> * * Contains definitions specific to the Armada XP SoC that are not * common to all Armada SoCs. */ #include "armada-370-xp.dtsi" / { #address-cells = <2>; #size-cells = <2>; model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; aliases { serial2 = &uart2; serial3 = &uart3; }; soc { compatible = "marvell,armadaxp-mbus", "simple-bus"; bootrom { compatible = "marvell,bootrom"; reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; }; internal-regs { sdramc@1400 { compatible = "marvell,armada-xp-sdram-controller"; reg = <0x1400 0x500>; }; L2: l2-cache@8000 { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; cache-level = <2>; cache-unified; wt-override; }; uart2: serial@12200 { compatible = "snps,dw-apb-uart"; pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; reg = <0x12200 0x100>; reg-shift = <2>; interrupts = <43>; reg-io-width = <1>; clocks = <&coreclk 0>; status = "disabled"; }; uart3: serial@12300 { compatible = "snps,dw-apb-uart"; pinctrl-0 = <&uart3_pins>; pinctrl-names = "default"; reg = <0x12300 0x100>; reg-shift = <2>; interrupts = <44>; reg-io-width = <1>; clocks = <&coreclk 0>; status = "disabled"; }; systemc: system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x500>; }; gateclk: clock-gating-control@18220 { compatible = "marvell,armada-xp-gating-clock"; reg = <0x18220 0x4>; clocks = <&coreclk 0>; #clock-cells = <1>; }; coreclk: mvebu-sar@18230 { compatible = "marvell,armada-xp-core-clock"; reg = <0x18230 0x08>; #clock-cells = <1>; }; thermal: thermal@182b0 { compatible = "marvell,armadaxp-thermal"; reg = <0x182b0 0x4 0x184d0 0x4>; status = "okay"; }; cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; reg = <0x18700 0x24>, <0x1c054 0x10>; clocks = <&coreclk 1>; }; cpu-config@21000 { compatible = "marvell,armada-xp-cpu-config"; reg = <0x21000 0x8>; }; eth2: ethernet@30000 { compatible = "marvell,armada-xp-neta"; reg = <0x30000 0x4000>; interrupts = <12>; clocks = <&gateclk 2>; status = "disabled"; }; usb2: usb@52000 { compatible = "marvell,orion-ehci"; reg = <0x52000 0x500>; interrupts = <47>; clocks = <&gateclk 20>; status = "disabled"; }; xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; clocks = <&gateclk 22>; status = "okay"; xor10 { interrupts = <51>; dmacap,memcpy; dmacap,xor; }; xor11 { interrupts = <52>; dmacap,memcpy; dmacap,xor; dmacap,memset; }; }; ethernet@70000 { compatible = "marvell,armada-xp-neta"; }; ethernet@74000 { compatible = "marvell,armada-xp-neta"; }; cesa: crypto@90000 { compatible = "marvell,armada-xp-crypto"; reg = <0x90000 0x10000>; reg-names = "regs"; interrupts = <48>, <49>; clocks = <&gateclk 23>, <&gateclk 23>; clock-names = "cesa0", "cesa1"; marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>; marvell,crypto-sram-size = <0x800>; }; bm: bm@c0000 { compatible = "marvell,armada-380-neta-bm"; reg = <0xc0000 0xac>; clocks = <&gateclk 13>; internal-mem = <&bm_bppi>; status = "disabled"; }; xor0: xor@f0900 { compatible = "marvell,orion-xor"; reg = <0xF0900 0x100 0xF0B00 0x100>; clocks = <&gateclk 28>; status = "okay"; xor00 { interrupts = <94>; dmacap,memcpy; dmacap,xor; }; xor01 { interrupts = <95>; dmacap,memcpy; dmacap,xor; dmacap,memset; }; }; }; crypto_sram0: sa-sram0 { compatible = "mmio-sram"; reg = <MBUS_ID(0x09, 0x09) 0 0x800>; clocks = <&gateclk 23>; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; }; crypto_sram1: sa-sram1 { compatible = "mmio-sram"; reg = <MBUS_ID(0x09, 0x05) 0 0x800>; clocks = <&gateclk 23>; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; }; bm_bppi: bm-bppi { compatible = "mmio-sram"; reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; #address-cells = <1>; #size-cells = <1>; clocks = <&gateclk 13>; no-memory-wc; status = "disabled"; }; }; clocks { /* 25 MHz reference crystal */ refclk: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; }; }; &i2c0 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; }; &i2c1 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11100 0x100>; }; &mpic { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; &timer { compatible = "marvell,armada-xp-timer"; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; &watchdog { compatible = "marvell,armada-xp-wdt"; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; &cpurst { reg = <0x20800 0x20>; }; &usb0 { clocks = <&gateclk 18>; }; &usb1 { clocks = <&gateclk 19>; }; &pinctrl { ge0_gmii_pins: ge0-gmii-pins { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17", "mpp18", "mpp19", "mpp20", "mpp21", "mpp22", "mpp23"; marvell,function = "ge0"; }; ge0_rgmii_pins: ge0-rgmii-pins { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11"; marvell,function = "ge0"; }; ge1_rgmii_pins: ge1-rgmii-pins { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17", "mpp18", "mpp19", "mpp20", "mpp21", "mpp22", "mpp23"; marvell,function = "ge1"; }; sdio_pins: sdio-pins { marvell,pins = "mpp30", "mpp31", "mpp32", "mpp33", "mpp34", "mpp35"; marvell,function = "sd0"; }; spi0_pins: spi0-pins { marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; marvell,function = "spi0"; }; spi1_pins: spi1-pins { marvell,pins = "mpp13", "mpp14", "mpp16", "mpp17"; marvell,function = "spi1"; }; uart2_pins: uart2-pins { marvell,pins = "mpp42", "mpp43"; marvell,function = "uart2"; }; uart3_pins: uart3-pins { marvell,pins = "mpp44", "mpp45"; marvell,function = "uart3"; }; }; &spi0 { compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; pinctrl-0 = <&spi0_pins>; pinctrl-names = "default"; }; &spi1 { compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; pinctrl-0 = <&spi1_pins>; pinctrl-names = "default"; }; |