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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 | /* * Copyright (c) 2016-2017 NVIDIA Corporation * * Author: Thierry Reding <treding@nvidia.com> * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. */ #include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/gpio/tegra186-gpio.h> #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) #define TEGRA186_GPIO_INPUT 0x08 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) struct tegra_gpio_port { const char *name; unsigned int offset; unsigned int pins; unsigned int irq; }; struct tegra_gpio_soc { const struct tegra_gpio_port *ports; unsigned int num_ports; const char *name; }; struct tegra_gpio { struct gpio_chip gpio; struct irq_chip intc; unsigned int num_irq; unsigned int *irq; const struct tegra_gpio_soc *soc; void __iomem *base; }; static const struct tegra_gpio_port * tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) { unsigned int start = 0, i; for (i = 0; i < gpio->soc->num_ports; i++) { const struct tegra_gpio_port *port = &gpio->soc->ports[i]; if (*pin >= start && *pin < start + port->pins) { *pin -= start; return port; } start += port->pins; } return NULL; } static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, unsigned int pin) { const struct tegra_gpio_port *port; port = tegra186_gpio_get_port(gpio, &pin); if (!port) return NULL; return gpio->base + port->offset + pin * 0x20; } static int tegra186_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct tegra_gpio *gpio = gpiochip_get_data(chip); void __iomem *base; u32 value; base = tegra186_gpio_get_base(gpio, offset); if (WARN_ON(base == NULL)) return -ENODEV; value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) return 0; return 1; } static int tegra186_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { struct tegra_gpio *gpio = gpiochip_get_data(chip); void __iomem *base; u32 value; base = tegra186_gpio_get_base(gpio, offset); if (WARN_ON(base == NULL)) return -ENODEV; value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); return 0; } static int tegra186_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int level) { struct tegra_gpio *gpio = gpiochip_get_data(chip); void __iomem *base; u32 value; /* configure output level first */ chip->set(chip, offset, level); base = tegra186_gpio_get_base(gpio, offset); if (WARN_ON(base == NULL)) return -EINVAL; /* set the direction */ value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); return 0; } static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct tegra_gpio *gpio = gpiochip_get_data(chip); void __iomem *base; u32 value; base = tegra186_gpio_get_base(gpio, offset); if (WARN_ON(base == NULL)) return -ENODEV; value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); else value = readl(base + TEGRA186_GPIO_INPUT); return value & BIT(0); } static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, int level) { struct tegra_gpio *gpio = gpiochip_get_data(chip); void __iomem *base; u32 value; base = tegra186_gpio_get_base(gpio, offset); if (WARN_ON(base == NULL)) return; value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); if (level == 0) value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; else value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); } static int tegra186_gpio_of_xlate(struct gpio_chip *chip, const struct of_phandle_args *spec, u32 *flags) { struct tegra_gpio *gpio = gpiochip_get_data(chip); unsigned int port, pin, i, offset = 0; if (WARN_ON(chip->of_gpio_n_cells < 2)) return -EINVAL; if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) return -EINVAL; port = spec->args[0] / 8; pin = spec->args[0] % 8; if (port >= gpio->soc->num_ports) { dev_err(chip->parent, "invalid port number: %u\n", port); return -EINVAL; } for (i = 0; i < port; i++) offset += gpio->soc->ports[i].pins; if (flags) *flags = spec->args[1]; return offset + pin; } static void tegra186_irq_ack(struct irq_data *data) { struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); void __iomem *base; base = tegra186_gpio_get_base(gpio, data->hwirq); if (WARN_ON(base == NULL)) return; writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); } static void tegra186_irq_mask(struct irq_data *data) { struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); void __iomem *base; u32 value; base = tegra186_gpio_get_base(gpio, data->hwirq); if (WARN_ON(base == NULL)) return; value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); } static void tegra186_irq_unmask(struct irq_data *data) { struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); void __iomem *base; u32 value; base = tegra186_gpio_get_base(gpio, data->hwirq); if (WARN_ON(base == NULL)) return; value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); } static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow) { struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); void __iomem *base; u32 value; base = tegra186_gpio_get_base(gpio, data->hwirq); if (WARN_ON(base == NULL)) return -ENODEV; value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; switch (flow & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_NONE: break; case IRQ_TYPE_EDGE_RISING: value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; break; case IRQ_TYPE_EDGE_FALLING: value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; break; case IRQ_TYPE_EDGE_BOTH: value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; break; case IRQ_TYPE_LEVEL_HIGH: value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; break; case IRQ_TYPE_LEVEL_LOW: value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; break; default: return -EINVAL; } writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); if ((flow & IRQ_TYPE_EDGE_BOTH) == 0) irq_set_handler_locked(data, handle_level_irq); else irq_set_handler_locked(data, handle_edge_irq); return 0; } static void tegra186_gpio_irq(struct irq_desc *desc) { struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); struct irq_domain *domain = gpio->gpio.irq.domain; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int parent = irq_desc_get_irq(desc); unsigned int i, offset = 0; chained_irq_enter(chip, desc); for (i = 0; i < gpio->soc->num_ports; i++) { const struct tegra_gpio_port *port = &gpio->soc->ports[i]; void __iomem *base = gpio->base + port->offset; unsigned int pin, irq; unsigned long value; /* skip ports that are not associated with this controller */ if (parent != gpio->irq[port->irq]) goto skip; value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); for_each_set_bit(pin, &value, port->pins) { irq = irq_find_mapping(domain, offset + pin); if (WARN_ON(irq == 0)) continue; generic_handle_irq(irq); } skip: offset += port->pins; } chained_irq_exit(chip, desc); } static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain, struct device_node *np, const u32 *spec, unsigned int size, unsigned long *hwirq, unsigned int *type) { struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); unsigned int port, pin, i, offset = 0; if (size < 2) return -EINVAL; port = spec[0] / 8; pin = spec[0] % 8; if (port >= gpio->soc->num_ports) { dev_err(gpio->gpio.parent, "invalid port number: %u\n", port); return -EINVAL; } for (i = 0; i < port; i++) offset += gpio->soc->ports[i].pins; *type = spec[1] & IRQ_TYPE_SENSE_MASK; *hwirq = offset + pin; return 0; } static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = { .map = gpiochip_irq_map, .unmap = gpiochip_irq_unmap, .xlate = tegra186_gpio_irq_domain_xlate, }; static int tegra186_gpio_probe(struct platform_device *pdev) { unsigned int i, j, offset; struct gpio_irq_chip *irq; struct tegra_gpio *gpio; struct resource *res; char **names; int err; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) return -ENOMEM; gpio->soc = of_device_get_match_data(&pdev->dev); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio"); gpio->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(gpio->base)) return PTR_ERR(gpio->base); err = platform_irq_count(pdev); if (err < 0) return err; gpio->num_irq = err; gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), GFP_KERNEL); if (!gpio->irq) return -ENOMEM; for (i = 0; i < gpio->num_irq; i++) { err = platform_get_irq(pdev, i); if (err < 0) return err; gpio->irq[i] = err; } gpio->gpio.label = gpio->soc->name; gpio->gpio.parent = &pdev->dev; gpio->gpio.get_direction = tegra186_gpio_get_direction; gpio->gpio.direction_input = tegra186_gpio_direction_input; gpio->gpio.direction_output = tegra186_gpio_direction_output; gpio->gpio.get = tegra186_gpio_get, gpio->gpio.set = tegra186_gpio_set; gpio->gpio.base = -1; for (i = 0; i < gpio->soc->num_ports; i++) gpio->gpio.ngpio += gpio->soc->ports[i].pins; names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, sizeof(*names), GFP_KERNEL); if (!names) return -ENOMEM; for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { const struct tegra_gpio_port *port = &gpio->soc->ports[i]; char *name; for (j = 0; j < port->pins; j++) { name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, "P%s.%02x", port->name, j); if (!name) return -ENOMEM; names[offset + j] = name; } offset += port->pins; } gpio->gpio.names = (const char * const *)names; gpio->gpio.of_node = pdev->dev.of_node; gpio->gpio.of_gpio_n_cells = 2; gpio->gpio.of_xlate = tegra186_gpio_of_xlate; gpio->intc.name = pdev->dev.of_node->name; gpio->intc.irq_ack = tegra186_irq_ack; gpio->intc.irq_mask = tegra186_irq_mask; gpio->intc.irq_unmask = tegra186_irq_unmask; gpio->intc.irq_set_type = tegra186_irq_set_type; irq = &gpio->gpio.irq; irq->chip = &gpio->intc; irq->domain_ops = &tegra186_gpio_irq_domain_ops; irq->handler = handle_simple_irq; irq->default_type = IRQ_TYPE_NONE; irq->parent_handler = tegra186_gpio_irq; irq->parent_handler_data = gpio; irq->num_parents = gpio->num_irq; irq->parents = gpio->irq; irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, sizeof(*irq->map), GFP_KERNEL); if (!irq->map) return -ENOMEM; for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { const struct tegra_gpio_port *port = &gpio->soc->ports[i]; for (j = 0; j < port->pins; j++) irq->map[offset + j] = irq->parents[port->irq]; offset += port->pins; } platform_set_drvdata(pdev, gpio); err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); if (err < 0) return err; return 0; } static int tegra186_gpio_remove(struct platform_device *pdev) { return 0; } #define TEGRA_MAIN_GPIO_PORT(port, base, count, controller) \ [TEGRA_MAIN_GPIO_PORT_##port] = { \ .name = #port, \ .offset = base, \ .pins = count, \ .irq = controller, \ } static const struct tegra_gpio_port tegra186_main_ports[] = { TEGRA_MAIN_GPIO_PORT( A, 0x2000, 7, 2), TEGRA_MAIN_GPIO_PORT( B, 0x3000, 7, 3), TEGRA_MAIN_GPIO_PORT( C, 0x3200, 7, 3), TEGRA_MAIN_GPIO_PORT( D, 0x3400, 6, 3), TEGRA_MAIN_GPIO_PORT( E, 0x2200, 8, 2), TEGRA_MAIN_GPIO_PORT( F, 0x2400, 6, 2), TEGRA_MAIN_GPIO_PORT( G, 0x4200, 6, 4), TEGRA_MAIN_GPIO_PORT( H, 0x1000, 7, 1), TEGRA_MAIN_GPIO_PORT( I, 0x0800, 8, 0), TEGRA_MAIN_GPIO_PORT( J, 0x5000, 8, 5), TEGRA_MAIN_GPIO_PORT( K, 0x5200, 1, 5), TEGRA_MAIN_GPIO_PORT( L, 0x1200, 8, 1), TEGRA_MAIN_GPIO_PORT( M, 0x5600, 6, 5), TEGRA_MAIN_GPIO_PORT( N, 0x0000, 7, 0), TEGRA_MAIN_GPIO_PORT( O, 0x0200, 4, 0), TEGRA_MAIN_GPIO_PORT( P, 0x4000, 7, 4), TEGRA_MAIN_GPIO_PORT( Q, 0x0400, 6, 0), TEGRA_MAIN_GPIO_PORT( R, 0x0a00, 6, 0), TEGRA_MAIN_GPIO_PORT( T, 0x0600, 4, 0), TEGRA_MAIN_GPIO_PORT( X, 0x1400, 8, 1), TEGRA_MAIN_GPIO_PORT( Y, 0x1600, 7, 1), TEGRA_MAIN_GPIO_PORT(BB, 0x2600, 2, 2), TEGRA_MAIN_GPIO_PORT(CC, 0x5400, 4, 5), }; static const struct tegra_gpio_soc tegra186_main_soc = { .num_ports = ARRAY_SIZE(tegra186_main_ports), .ports = tegra186_main_ports, .name = "tegra186-gpio", }; #define TEGRA_AON_GPIO_PORT(port, base, count, controller) \ [TEGRA_AON_GPIO_PORT_##port] = { \ .name = #port, \ .offset = base, \ .pins = count, \ .irq = controller, \ } static const struct tegra_gpio_port tegra186_aon_ports[] = { TEGRA_AON_GPIO_PORT( S, 0x0200, 5, 0), TEGRA_AON_GPIO_PORT( U, 0x0400, 6, 0), TEGRA_AON_GPIO_PORT( V, 0x0800, 8, 0), TEGRA_AON_GPIO_PORT( W, 0x0a00, 8, 0), TEGRA_AON_GPIO_PORT( Z, 0x0e00, 4, 0), TEGRA_AON_GPIO_PORT(AA, 0x0c00, 8, 0), TEGRA_AON_GPIO_PORT(EE, 0x0600, 3, 0), TEGRA_AON_GPIO_PORT(FF, 0x0000, 5, 0), }; static const struct tegra_gpio_soc tegra186_aon_soc = { .num_ports = ARRAY_SIZE(tegra186_aon_ports), .ports = tegra186_aon_ports, .name = "tegra186-gpio-aon", }; static const struct of_device_id tegra186_gpio_of_match[] = { { .compatible = "nvidia,tegra186-gpio", .data = &tegra186_main_soc }, { .compatible = "nvidia,tegra186-gpio-aon", .data = &tegra186_aon_soc }, { /* sentinel */ } }; static struct platform_driver tegra186_gpio_driver = { .driver = { .name = "tegra186-gpio", .of_match_table = tegra186_gpio_of_match, }, .probe = tegra186_gpio_probe, .remove = tegra186_gpio_remove, }; module_platform_driver(tegra186_gpio_driver); MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); MODULE_LICENSE("GPL v2"); |