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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 | /* * DTS File for HiSilicon Hi3798cv200 SoC. * * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. * * Released under the GPLv2 only. * SPDX-License-Identifier: GPL-2.0 */ #include <dt-bindings/clock/histb-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/ti-syscon.h> / { compatible = "hisilicon,hi3798cv200"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; psci { compatible = "arm,psci-0.2"; method = "smc"; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; }; cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; }; cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; }; cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; }; }; gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ <0x0 0xf1002000 0x0 0x100>; /* GICC */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; soc: soc@f0000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0xf0000000 0x10000000>; crg: clock-reset-controller@8a22000 { compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; reg = <0x8a22000 0x1000>; #clock-cells = <1>; #reset-cells = <2>; gmacphyrst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET|STATUS_NONE)>, <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET|STATUS_NONE)>; }; }; sysctrl: system-controller@8000000 { compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; reg = <0x8000000 0x1000>; #clock-cells = <1>; #reset-cells = <2>; }; uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sysctrl HISTB_UART0_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; uart2: serial@8b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b02000 0x1000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HISTB_UART2_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; i2c0: i2c@8b10000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0x8b10000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; clocks = <&crg HISTB_I2C0_CLK>; status = "disabled"; }; i2c1: i2c@8b11000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0x8b11000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; clocks = <&crg HISTB_I2C1_CLK>; status = "disabled"; }; i2c2: i2c@8b12000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0x8b12000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; clocks = <&crg HISTB_I2C2_CLK>; status = "disabled"; }; i2c3: i2c@8b13000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0x8b13000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; clocks = <&crg HISTB_I2C3_CLK>; status = "disabled"; }; i2c4: i2c@8b14000 { compatible = "hisilicon,hix5hd2-i2c"; reg = <0x8b14000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <400000>; clocks = <&crg HISTB_I2C4_CLK>; status = "disabled"; }; spi0: spi@8b1a000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x8b1a000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; num-cs = <1>; cs-gpios = <&gpio7 1 0>; clocks = <&crg HISTB_SPI0_CLK>; clock-names = "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; sd0: mmc@9820000 { compatible = "snps,dw-mshc"; reg = <0x9820000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HISTB_SDIO0_CIU_CLK>, <&crg HISTB_SDIO0_BIU_CLK>; clock-names = "ciu", "biu"; resets = <&crg 0x9c 4>; reset-names = "reset"; status = "disabled"; }; emmc: mmc@9830000 { compatible = "snps,dw-mshc"; reg = <0x9830000 0x10000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HISTB_MMC_CIU_CLK>, <&crg HISTB_MMC_BIU_CLK>; clock-names = "ciu", "biu"; }; gpio0: gpio@8b20000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b20000 0x1000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio1: gpio@8b21000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b21000 0x1000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio2: gpio@8b22000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b22000 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio3: gpio@8b23000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b23000 0x1000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio4: gpio@8b24000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b24000 0x1000>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio5: gpio@8004000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8004000 0x1000>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio6: gpio@8b26000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b26000 0x1000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio7: gpio@8b27000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b27000 0x1000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio8: gpio@8b28000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b28000 0x1000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio9: gpio@8b29000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b29000 0x1000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio10: gpio@8b2a000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b2a000 0x1000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio11: gpio@8b2b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b2b000 0x1000>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gpio12: gpio@8b2c000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x8b2c000 0x1000>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; }; gmac0: ethernet@9840000 { compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; reg = <0x9840000 0x1000>, <0x984300c 0x4>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>; clock-names = "mac_core", "mac_ifc"; resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&gmacphyrst 0>; reset-names = "mac_core", "mac_ifc", "phy"; status = "disabled"; }; gmac1: ethernet@9841000 { compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; reg = <0x9841000 0x1000>, <0x9843010 0x4>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HISTB_ETH1_MAC_CLK>, <&crg HISTB_ETH1_MACIF_CLK>; clock-names = "mac_core", "mac_ifc"; resets = <&crg 0xcc 9>, <&crg 0xcc 11>, <&gmacphyrst 1>; reset-names = "mac_core", "mac_ifc", "phy"; status = "disabled"; }; ir: ir@8001000 { compatible = "hisilicon,hix5hd2-ir"; reg = <0x8001000 0x1000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sysctrl HISTB_IR_CLK>; status = "disabled"; }; }; }; |