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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 | // SPDX-License-Identifier: GPL-2.0 /* * Allocator for I/O pins. All pins are allocated to GPIO at bootup. * Unassigned pins and GPIO pins can be allocated to a fixed interface * or the I/O processor instead. * * Copyright (c) 2005-2007 Axis Communications AB. */ #include <linux/init.h> #include <linux/errno.h> #include <linux/kernel.h> #include <linux/string.h> #include <linux/spinlock.h> #include <hwregs/reg_map.h> #include <hwregs/reg_rdwr.h> #include <pinmux.h> #include <hwregs/pinmux_defs.h> #include <hwregs/clkgen_defs.h> #undef DEBUG #define PINS 80 #define PORT_PINS 32 #define PORTS 3 static char pins[PINS]; static DEFINE_SPINLOCK(pinmux_lock); static void crisv32_pinmux_set(int port); int crisv32_pinmux_init(void) { static int initialized; if (!initialized) { initialized = 1; REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio); crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio); crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio); } return 0; } int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode) { int i; unsigned long flags; crisv32_pinmux_init(); if (port >= PORTS) return -EINVAL; spin_lock_irqsave(&pinmux_lock, flags); for (i = first_pin; i <= last_pin; i++) { if ((pins[port * PORT_PINS + i] != pinmux_none) && (pins[port * PORT_PINS + i] != pinmux_gpio) && (pins[port * PORT_PINS + i] != mode)) { spin_unlock_irqrestore(&pinmux_lock, flags); #ifdef DEBUG panic("Pinmux alloc failed!\n"); #endif return -EPERM; } } for (i = first_pin; i <= last_pin; i++) pins[port * PORT_PINS + i] = mode; crisv32_pinmux_set(port); spin_unlock_irqrestore(&pinmux_lock, flags); return 0; } int crisv32_pinmux_alloc_fixed(enum fixed_function function) { int ret = -EINVAL; char saved[sizeof pins]; unsigned long flags; reg_pinmux_rw_hwprot hwprot; reg_clkgen_rw_clk_ctrl clk_ctrl; spin_lock_irqsave(&pinmux_lock, flags); /* Save internal data for recovery */ memcpy(saved, pins, sizeof pins); crisv32_pinmux_init(); /* must be done before we read rw_hwprot */ hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); switch (function) { case pinmux_eth: clk_ctrl.eth = regk_clkgen_yes; clk_ctrl.dma0_1_eth = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed); ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed); hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes; break; case pinmux_geth: ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed); hwprot.geth = regk_pinmux_yes; break; case pinmux_tg_cmos: clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed); hwprot.tg_clk = regk_pinmux_yes; break; case pinmux_tg_ccd: clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed); ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed); hwprot.tg = hwprot.tg_clk = regk_pinmux_yes; break; case pinmux_vout: clk_ctrl.strdma0_2_video = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed); hwprot.vout = hwprot.vout_sync = regk_pinmux_yes; break; case pinmux_ser1: clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed); hwprot.ser1 = regk_pinmux_yes; break; case pinmux_ser2: clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed); hwprot.ser2 = regk_pinmux_yes; break; case pinmux_ser3: clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed); hwprot.ser3 = regk_pinmux_yes; break; case pinmux_ser4: clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed); hwprot.ser4 = regk_pinmux_yes; break; case pinmux_sser: clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed); hwprot.sser = regk_pinmux_yes; break; case pinmux_pio: hwprot.pio = regk_pinmux_yes; ret = 0; break; case pinmux_pwm0: ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed); hwprot.pwm0 = regk_pinmux_yes; break; case pinmux_pwm1: ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed); hwprot.pwm1 = regk_pinmux_yes; break; case pinmux_pwm2: ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed); hwprot.pwm2 = regk_pinmux_yes; break; case pinmux_i2c0: ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed); hwprot.i2c0 = regk_pinmux_yes; break; case pinmux_i2c1: ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); hwprot.i2c1 = regk_pinmux_yes; break; case pinmux_i2c1_3wire: ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed); hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes; break; case pinmux_i2c1_sda1: ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed); hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes; break; case pinmux_i2c1_sda2: ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed); hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes; break; case pinmux_i2c1_sda3: ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed); hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes; break; default: ret = -EINVAL; break; } if (!ret) { REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); } else memcpy(pins, saved, sizeof pins); spin_unlock_irqrestore(&pinmux_lock, flags); return ret; } void crisv32_pinmux_set(int port) { int i; int gpio_val = 0; int iop_val = 0; int pin = port * PORT_PINS; for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) { if (pins[pin] == pinmux_gpio) gpio_val |= (1 << i); else if (pins[pin] == pinmux_iop) iop_val |= (1 << i); } REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port, gpio_val); REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port, iop_val); #ifdef DEBUG crisv32_pinmux_dump(); #endif } int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) { int i; unsigned long flags; crisv32_pinmux_init(); if (port > PORTS || port < 0) return -EINVAL; spin_lock_irqsave(&pinmux_lock, flags); for (i = first_pin; i <= last_pin; i++) pins[port * PORT_PINS + i] = pinmux_none; crisv32_pinmux_set(port); spin_unlock_irqrestore(&pinmux_lock, flags); return 0; } int crisv32_pinmux_dealloc_fixed(enum fixed_function function) { int ret = -EINVAL; char saved[sizeof pins]; unsigned long flags; reg_pinmux_rw_hwprot hwprot; spin_lock_irqsave(&pinmux_lock, flags); /* Save internal data for recovery */ memcpy(saved, pins, sizeof pins); crisv32_pinmux_init(); /* must be done before we read rw_hwprot */ hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); switch (function) { case pinmux_eth: ret = crisv32_pinmux_dealloc(PORT_B, 8, 23); ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25); ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7); hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no; break; case pinmux_tg_cmos: ret = crisv32_pinmux_dealloc(PORT_B, 27, 29); hwprot.tg_clk = regk_pinmux_no; break; case pinmux_tg_ccd: ret = crisv32_pinmux_dealloc(PORT_B, 27, 31); ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15); hwprot.tg = hwprot.tg_clk = regk_pinmux_no; break; case pinmux_vout: ret = crisv32_pinmux_dealloc(PORT_A, 8, 18); hwprot.vout = hwprot.vout_sync = regk_pinmux_no; break; case pinmux_ser1: ret = crisv32_pinmux_dealloc(PORT_A, 24, 25); hwprot.ser1 = regk_pinmux_no; break; case pinmux_ser2: ret = crisv32_pinmux_dealloc(PORT_A, 26, 27); hwprot.ser2 = regk_pinmux_no; break; case pinmux_ser3: ret = crisv32_pinmux_dealloc(PORT_A, 28, 29); hwprot.ser3 = regk_pinmux_no; break; case pinmux_ser4: ret = crisv32_pinmux_dealloc(PORT_A, 30, 31); hwprot.ser4 = regk_pinmux_no; break; case pinmux_sser: ret = crisv32_pinmux_dealloc(PORT_A, 19, 23); hwprot.sser = regk_pinmux_no; break; case pinmux_pwm0: ret = crisv32_pinmux_dealloc(PORT_A, 30, 30); hwprot.pwm0 = regk_pinmux_no; break; case pinmux_pwm1: ret = crisv32_pinmux_dealloc(PORT_A, 31, 31); hwprot.pwm1 = regk_pinmux_no; break; case pinmux_pwm2: ret = crisv32_pinmux_dealloc(PORT_B, 26, 26); hwprot.pwm2 = regk_pinmux_no; break; case pinmux_i2c0: ret = crisv32_pinmux_dealloc(PORT_A, 0, 1); hwprot.i2c0 = regk_pinmux_no; break; case pinmux_i2c1: ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); hwprot.i2c1 = regk_pinmux_no; break; case pinmux_i2c1_3wire: ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7); hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no; break; case pinmux_i2c1_sda1: ret = crisv32_pinmux_dealloc(PORT_A, 2, 4); hwprot.i2c1_sda1 = regk_pinmux_no; break; case pinmux_i2c1_sda2: ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5); hwprot.i2c1_sda2 = regk_pinmux_no; break; case pinmux_i2c1_sda3: ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6); hwprot.i2c1_sda3 = regk_pinmux_no; break; default: ret = -EINVAL; break; } if (!ret) REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); else memcpy(pins, saved, sizeof pins); spin_unlock_irqrestore(&pinmux_lock, flags); return ret; } void crisv32_pinmux_dump(void) { int i, j; int pin = 0; crisv32_pinmux_init(); for (i = 0; i < PORTS; i++) { pin++; printk(KERN_DEBUG "Port %c\n", 'A'+i); for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++) printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i * PORT_PINS + j]); } } __initcall(crisv32_pinmux_init); |