/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 * Copyright 2016 Toradex AG
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "imx7s.dtsi"
#include <dt-bindings/reset/imx7-reset.h>

/ {
	cpus {
		cpu0: cpu@0 {
			operating-points = <
				/* KHz	uV */
				996000	1075000
				792000	975000
			>;
			clock-frequency = <996000000>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
			clock-frequency = <996000000>;
		};
	};

	soc {
		etm@3007d000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x3007d000 0x1000>;

			/*
			 * System will hang if added nosmp in kernel command line
			 * without arm,primecell-periphid because amba bus try to
			 * read id and core1 power off at this time.
			 */
			arm,primecell-periphid = <0xbb956>;
			cpu = <&cpu1>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			port {
				etm1_out_port: endpoint {
					remote-endpoint = <&ca_funnel_in_port1>;
				};
			};
		};
	};
};

&aips3 {
	usbotg2: usb@30b20000 {
		compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
		reg = <0x30b20000 0x200>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_USB_CTRL_CLK>;
		fsl,usbphy = <&usbphynop2>;
		fsl,usbmisc = <&usbmisc2 0>;
		phy-clkgate-delay-us = <400>;
		status = "disabled";
	};

	usbmisc2: usbmisc@30b20200 {
		#index-cells = <1>;
		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
		reg = <0x30b20200 0x200>;
	};

	usbphynop2: usbphynop2 {
		compatible = "usb-nop-xceiv";
		clocks = <&clks IMX7D_USB_PHY2_CLK>;
		clock-names = "main_clk";
	};

	fec2: ethernet@30bf0000 {
		compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
		reg = <0x30bf0000 0x10000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
			<&clks IMX7D_ENET_AXI_ROOT_CLK>,
			<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
			<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
			<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
		clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		status = "disabled";
	};

	pcie: pcie@0x33800000 {
		compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
		reg = <0x33800000 0x4000>,
		      <0x4ff00000 0x80000>;
		reg-names = "dbi", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
		num-lanes = <1>;
		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		/*
		 * Reference manual lists pci irqs incorrectly
		 * Real hardware ordering is same as imx6: D+MSI, C, B, A
		 */
		interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
			 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
			 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
		clock-names = "pcie", "pcie_bus", "pcie_phy";
		assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
				  <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
		assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
					 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;

		fsl,max-link-speed = <2>;
		power-domains = <&pgc_pcie_phy>;
		resets = <&src IMX7_RESET_PCIEPHY>,
			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
		reset-names = "pciephy", "apps";
		status = "disabled";
	};
};

&ca_funnel_ports {
	port@1 {
		reg = <1>;
		ca_funnel_in_port1: endpoint {
			slave-mode;
			remote-endpoint = <&etm1_out_port>;
		};
	};
};