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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 | /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ser_defs_h #define __ser_defs_h /* * This file is autogenerated from * file: ../../inst/ser/rtl/ser_regs.r * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp * last modfied: Mon Apr 11 16:09:21 2005 * * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ * Any changes here will be lost. * * -*- buffer-read-only: t -*- */ /* Main access macros */ #ifndef REG_RD #define REG_RD( scope, inst, reg ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR #define REG_WR( scope, inst, reg, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_VECT #define REG_RD_VECT( scope, inst, reg, index ) \ REG_READ( reg_##scope##_##reg, \ (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_VECT #define REG_WR_VECT( scope, inst, reg, index, val ) \ REG_WRITE( reg_##scope##_##reg, \ (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT #define REG_RD_INT( scope, inst, reg ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_WR_INT #define REG_WR_INT( scope, inst, reg, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) #endif #ifndef REG_RD_INT_VECT #define REG_RD_INT_VECT( scope, inst, reg, index ) \ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif #ifndef REG_WR_INT_VECT #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg, (val) ) #endif #ifndef REG_TYPE_CONV #define REG_TYPE_CONV( type, orgtype, val ) \ ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) #endif #ifndef reg_page_size #define reg_page_size 8192 #endif #ifndef REG_ADDR #define REG_ADDR( scope, inst, reg ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg ) #endif #ifndef REG_ADDR_VECT #define REG_ADDR_VECT( scope, inst, reg, index ) \ ( (inst) + REG_RD_ADDR_##scope##_##reg + \ (index) * STRIDE_##scope##_##reg ) #endif /* C-code for register scope ser */ /* Register rw_tr_ctrl, scope ser, type rw */ typedef struct { unsigned int base_freq : 3; unsigned int en : 1; unsigned int par : 2; unsigned int par_en : 1; unsigned int data_bits : 1; unsigned int stop_bits : 1; unsigned int stop : 1; unsigned int rts_delay : 3; unsigned int rts_setup : 1; unsigned int auto_rts : 1; unsigned int txd : 1; unsigned int auto_cts : 1; unsigned int dummy1 : 15; } reg_ser_rw_tr_ctrl; #define REG_RD_ADDR_ser_rw_tr_ctrl 0 #define REG_WR_ADDR_ser_rw_tr_ctrl 0 /* Register rw_tr_dma_en, scope ser, type rw */ typedef struct { unsigned int en : 1; unsigned int dummy1 : 31; } reg_ser_rw_tr_dma_en; #define REG_RD_ADDR_ser_rw_tr_dma_en 4 #define REG_WR_ADDR_ser_rw_tr_dma_en 4 /* Register rw_rec_ctrl, scope ser, type rw */ typedef struct { unsigned int base_freq : 3; unsigned int en : 1; unsigned int par : 2; unsigned int par_en : 1; unsigned int data_bits : 1; unsigned int dma_mode : 1; unsigned int dma_err : 1; unsigned int sampling : 1; unsigned int timeout : 3; unsigned int auto_eop : 1; unsigned int half_duplex : 1; unsigned int rts_n : 1; unsigned int loopback : 1; unsigned int dummy1 : 14; } reg_ser_rw_rec_ctrl; #define REG_RD_ADDR_ser_rw_rec_ctrl 8 #define REG_WR_ADDR_ser_rw_rec_ctrl 8 /* Register rw_tr_baud_div, scope ser, type rw */ typedef struct { unsigned int div : 16; unsigned int dummy1 : 16; } reg_ser_rw_tr_baud_div; #define REG_RD_ADDR_ser_rw_tr_baud_div 12 #define REG_WR_ADDR_ser_rw_tr_baud_div 12 /* Register rw_rec_baud_div, scope ser, type rw */ typedef struct { unsigned int div : 16; unsigned int dummy1 : 16; } reg_ser_rw_rec_baud_div; #define REG_RD_ADDR_ser_rw_rec_baud_div 16 #define REG_WR_ADDR_ser_rw_rec_baud_div 16 /* Register rw_xoff, scope ser, type rw */ typedef struct { unsigned int chr : 8; unsigned int automatic : 1; unsigned int dummy1 : 23; } reg_ser_rw_xoff; #define REG_RD_ADDR_ser_rw_xoff 20 #define REG_WR_ADDR_ser_rw_xoff 20 /* Register rw_xoff_clr, scope ser, type rw */ typedef struct { unsigned int clr : 1; unsigned int dummy1 : 31; } reg_ser_rw_xoff_clr; #define REG_RD_ADDR_ser_rw_xoff_clr 24 #define REG_WR_ADDR_ser_rw_xoff_clr 24 /* Register rw_dout, scope ser, type rw */ typedef struct { unsigned int data : 8; unsigned int dummy1 : 24; } reg_ser_rw_dout; #define REG_RD_ADDR_ser_rw_dout 28 #define REG_WR_ADDR_ser_rw_dout 28 /* Register rs_stat_din, scope ser, type rs */ typedef struct { unsigned int data : 8; unsigned int dummy1 : 8; unsigned int dav : 1; unsigned int framing_err : 1; unsigned int par_err : 1; unsigned int orun : 1; unsigned int rec_err : 1; unsigned int rxd : 1; unsigned int tr_idle : 1; unsigned int tr_empty : 1; unsigned int tr_rdy : 1; unsigned int cts_n : 1; unsigned int xoff_detect : 1; unsigned int rts_n : 1; unsigned int txd : 1; unsigned int dummy2 : 3; } reg_ser_rs_stat_din; #define REG_RD_ADDR_ser_rs_stat_din 32 /* Register r_stat_din, scope ser, type r */ typedef struct { unsigned int data : 8; unsigned int dummy1 : 8; unsigned int dav : 1; unsigned int framing_err : 1; unsigned int par_err : 1; unsigned int orun : 1; unsigned int rec_err : 1; unsigned int rxd : 1; unsigned int tr_idle : 1; unsigned int tr_empty : 1; unsigned int tr_rdy : 1; unsigned int cts_n : 1; unsigned int xoff_detect : 1; unsigned int rts_n : 1; unsigned int txd : 1; unsigned int dummy2 : 3; } reg_ser_r_stat_din; #define REG_RD_ADDR_ser_r_stat_din 36 /* Register rw_rec_eop, scope ser, type rw */ typedef struct { unsigned int set : 1; unsigned int dummy1 : 31; } reg_ser_rw_rec_eop; #define REG_RD_ADDR_ser_rw_rec_eop 40 #define REG_WR_ADDR_ser_rw_rec_eop 40 /* Register rw_intr_mask, scope ser, type rw */ typedef struct { unsigned int tr_rdy : 1; unsigned int tr_empty : 1; unsigned int tr_idle : 1; unsigned int dav : 1; unsigned int dummy1 : 28; } reg_ser_rw_intr_mask; #define REG_RD_ADDR_ser_rw_intr_mask 44 #define REG_WR_ADDR_ser_rw_intr_mask 44 /* Register rw_ack_intr, scope ser, type rw */ typedef struct { unsigned int tr_rdy : 1; unsigned int tr_empty : 1; unsigned int tr_idle : 1; unsigned int dav : 1; unsigned int dummy1 : 28; } reg_ser_rw_ack_intr; #define REG_RD_ADDR_ser_rw_ack_intr 48 #define REG_WR_ADDR_ser_rw_ack_intr 48 /* Register r_intr, scope ser, type r */ typedef struct { unsigned int tr_rdy : 1; unsigned int tr_empty : 1; unsigned int tr_idle : 1; unsigned int dav : 1; unsigned int dummy1 : 28; } reg_ser_r_intr; #define REG_RD_ADDR_ser_r_intr 52 /* Register r_masked_intr, scope ser, type r */ typedef struct { unsigned int tr_rdy : 1; unsigned int tr_empty : 1; unsigned int tr_idle : 1; unsigned int dav : 1; unsigned int dummy1 : 28; } reg_ser_r_masked_intr; #define REG_RD_ADDR_ser_r_masked_intr 56 /* Constants */ enum { regk_ser_active = 0x00000000, regk_ser_bits1 = 0x00000000, regk_ser_bits2 = 0x00000001, regk_ser_bits7 = 0x00000001, regk_ser_bits8 = 0x00000000, regk_ser_del0_5 = 0x00000000, regk_ser_del1 = 0x00000001, regk_ser_del1_5 = 0x00000002, regk_ser_del2 = 0x00000003, regk_ser_del2_5 = 0x00000004, regk_ser_del3 = 0x00000005, regk_ser_del3_5 = 0x00000006, regk_ser_del4 = 0x00000007, regk_ser_even = 0x00000000, regk_ser_ext = 0x00000001, regk_ser_f100 = 0x00000007, regk_ser_f29_493 = 0x00000004, regk_ser_f32 = 0x00000005, regk_ser_f32_768 = 0x00000006, regk_ser_ignore = 0x00000001, regk_ser_inactive = 0x00000001, regk_ser_majority = 0x00000001, regk_ser_mark = 0x00000002, regk_ser_middle = 0x00000000, regk_ser_no = 0x00000000, regk_ser_odd = 0x00000001, regk_ser_off = 0x00000000, regk_ser_rw_intr_mask_default = 0x00000000, regk_ser_rw_rec_baud_div_default = 0x00000000, regk_ser_rw_rec_ctrl_default = 0x00010000, regk_ser_rw_tr_baud_div_default = 0x00000000, regk_ser_rw_tr_ctrl_default = 0x00008000, regk_ser_rw_tr_dma_en_default = 0x00000000, regk_ser_rw_xoff_default = 0x00000000, regk_ser_space = 0x00000003, regk_ser_stop = 0x00000000, regk_ser_yes = 0x00000001 }; #endif /* __ser_defs_h */ |