/*
 * Samsung's Exynos5 SoC series common device tree source
 *
 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
 * SoCs from Exynos5 series can include this file and provide values for SoCs
 * specfic bindings.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		serial0 = &serial_0;
		serial1 = &serial_1;
		serial2 = &serial_2;
		serial3 = &serial_3;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		sromc: memory-controller@12250000 {
			compatible = "samsung,exynos4210-srom";
			reg = <0x12250000 0x14>;
		};

		combiner: interrupt-controller@10440000 {
			compatible = "samsung,exynos4210-combiner";
			#interrupt-cells = <2>;
			interrupt-controller;
			samsung,combiner-nr = <32>;
			reg = <0x10440000 0x1000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@10481000 {
			compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg =	<0x10481000 0x1000>,
				<0x10482000 0x2000>,
				<0x10484000 0x2000>,
				<0x10486000 0x2000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		sysreg_system_controller: syscon@10050000 {
			compatible = "samsung,exynos5-sysreg", "syscon";
			reg = <0x10050000 0x5000>;
		};

		serial_0: serial@12C00000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C00000 0x100>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial_1: serial@12C10000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C10000 0x100>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial_2: serial@12C20000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C20000 0x100>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		};

		serial_3: serial@12C30000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x12C30000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		};

		i2c_0: i2c@12C60000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C60000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		i2c_1: i2c@12C70000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C70000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		i2c_2: i2c@12C80000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C80000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		i2c_3: i2c@12C90000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x12C90000 0x100>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			samsung,sysreg-phandle = <&sysreg_system_controller>;
			status = "disabled";
		};

		pwm: pwm@12DD0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x12DD0000 0x100>;
			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
			#pwm-cells = <3>;
		};

		rtc: rtc@101E0000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x101E0000 0x100>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		fimd: fimd@14400000 {
			compatible = "samsung,exynos5250-fimd";
			interrupt-parent = <&combiner>;
			reg = <0x14400000 0x40000>;
			interrupt-names = "fifo", "vsync", "lcd_sys";
			interrupts = <18 4>, <18 5>, <18 6>;
			samsung,sysreg = <&sysreg_system_controller>;
			status = "disabled";
		};

		dp: dp-controller@145B0000 {
			compatible = "samsung,exynos5-dp";
			reg = <0x145B0000 0x1000>;
			interrupts = <10 3>;
			interrupt-parent = <&combiner>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};
};