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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 | /* * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 * as published by the Free Software Foundation * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef __MT7601U_DMA_H #define __MT7601U_DMA_H #include <asm/unaligned.h> #include <linux/skbuff.h> #define MT_DMA_HDR_LEN 4 #define MT_RX_INFO_LEN 4 #define MT_FCE_INFO_LEN 4 #define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN) /* Common Tx DMA descriptor fields */ #define MT_TXD_INFO_LEN GENMASK(15, 0) #define MT_TXD_INFO_D_PORT GENMASK(29, 27) #define MT_TXD_INFO_TYPE GENMASK(31, 30) enum mt76_msg_port { WLAN_PORT, CPU_RX_PORT, CPU_TX_PORT, HOST_PORT, VIRTUAL_CPU_RX_PORT, VIRTUAL_CPU_TX_PORT, DISCARD, }; enum mt76_info_type { DMA_PACKET, DMA_COMMAND, }; /* Tx DMA packet specific flags */ #define MT_TXD_PKT_INFO_NEXT_VLD BIT(16) #define MT_TXD_PKT_INFO_TX_BURST BIT(17) #define MT_TXD_PKT_INFO_80211 BIT(19) #define MT_TXD_PKT_INFO_TSO BIT(20) #define MT_TXD_PKT_INFO_CSO BIT(21) #define MT_TXD_PKT_INFO_WIV BIT(24) #define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25) enum mt76_qsel { MT_QSEL_MGMT, MT_QSEL_HCCA, MT_QSEL_EDCA, MT_QSEL_EDCA_2, }; /* Tx DMA MCU command specific flags */ #define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16) #define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20) static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb, enum mt76_msg_port d_port, enum mt76_info_type type, u32 flags) { u32 info; /* Buffer layout: * | 4B | xfer len | pad | 4B | * | TXINFO | pkt/cmd | zero pad to 4B | zero | * * length field of TXINFO should be set to 'xfer len'. */ info = flags | FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) | FIELD_PREP(MT_TXD_INFO_D_PORT, d_port) | FIELD_PREP(MT_TXD_INFO_TYPE, type); put_unaligned_le32(info, skb_push(skb, sizeof(info))); return skb_put_padto(skb, round_up(skb->len, 4) + 4); } static inline int mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags) { flags |= FIELD_PREP(MT_TXD_PKT_INFO_QSEL, qsel); return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags); } /* Common Rx DMA descriptor fields */ #define MT_RXD_INFO_LEN GENMASK(13, 0) #define MT_RXD_INFO_PCIE_INTR BIT(24) #define MT_RXD_INFO_QSEL GENMASK(26, 25) #define MT_RXD_INFO_PORT GENMASK(29, 27) #define MT_RXD_INFO_TYPE GENMASK(31, 30) /* Rx DMA packet specific flags */ #define MT_RXD_PKT_INFO_UDP_ERR BIT(16) #define MT_RXD_PKT_INFO_TCP_ERR BIT(17) #define MT_RXD_PKT_INFO_IP_ERR BIT(18) #define MT_RXD_PKT_INFO_PKT_80211 BIT(19) #define MT_RXD_PKT_INFO_L3L4_DONE BIT(20) #define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21) /* Rx DMA MCU command specific flags */ #define MT_RXD_CMD_INFO_SELF_GEN BIT(15) #define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16) #define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20) enum mt76_evt_type { CMD_DONE, CMD_ERROR, CMD_RETRY, EVENT_PWR_RSP, EVENT_WOW_RSP, EVENT_CARRIER_DETECT_RSP, EVENT_DFS_DETECT_RSP, }; #endif |