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 *
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 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
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 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
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 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/clock/bcm-sr.h>

		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		crmu_ref25m: crmu_ref25m {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&osc>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		genpll0: genpll0@0001d104 {
			#clock-cells = <1>;
			compatible = "brcm,sr-genpll0";
			reg = <0x0001d104 0x32>,
			      <0x0001c854 0x4>;
			clocks = <&osc>;
			clock-output-names = "genpll0", "clk_125", "clk_scr",
					     "clk_250", "clk_pcie_axi",
					     "clk_paxc_axi_x2",
					     "clk_paxc_axi";
		};

		genpll3: genpll3@0001d1e0 {
			#clock-cells = <1>;
			compatible = "brcm,sr-genpll3";
			reg = <0x0001d1e0 0x32>,
			      <0x0001c854 0x4>;
			clocks = <&osc>;
			clock-output-names = "genpll3", "clk_hsls",
					     "clk_sdio";
		};

		genpll4: genpll4@0001d214 {
			#clock-cells = <1>;
			compatible = "brcm,sr-genpll4";
			reg = <0x0001d214 0x32>,
			      <0x0001c854 0x4>;
			clocks = <&osc>;
			clock-output-names = "genpll4", "clk_ccn",
					     "clk_tpiu_pll", "noc_clk",
					     "pll_chclk_fs4",
					     "clk_bridge_fscpu";
		};

		genpll5: genpll5@0001d248 {
			#clock-cells = <1>;
			compatible = "brcm,sr-genpll5";
			reg = <0x0001d248 0x32>,
			      <0x0001c870 0x4>;
			clocks = <&osc>;
			clock-output-names = "genpll5", "fs4_hf_clk",
					     "crypto_ae_clk", "raid_ae_clk";
		};

		lcpll0: lcpll0@0001d0c4 {
			#clock-cells = <1>;
			compatible = "brcm,sr-lcpll0";
			reg = <0x0001d0c4 0x3c>,
			      <0x0001c870 0x4>;
			clocks = <&osc>;
			clock-output-names = "lcpll0", "clk_sata_refp",
					     "clk_sata_refn", "clk_sata_350",
					     "clk_sata_500";
		};

		lcpll1: lcpll1@0001d138 {
			#clock-cells = <1>;
			compatible = "brcm,sr-lcpll1";
			reg = <0x0001d138 0x3c>,
			      <0x0001c870 0x4>;
			clocks = <&osc>;
			clock-output-names = "lcpll1", "clk_wanpn",
					     "clk_usb_ref",
					     "timesync_evt_clk";
		};

		hsls_clk: hsls_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll3 1>;
			clock-div = <1>;
			clock-mult = <1>;
		};

		hsls_div2_clk: hsls_div2_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
			clock-div = <2>;
			clock-mult = <1>;

		};

		hsls_div4_clk: hsls_div4_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
			clock-div = <4>;
			clock-mult = <1>;
		};

		hsls_25m_clk: hsls_25m_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&crmu_ref25m>;
			clock-div = <1>;
			clock-mult = <1>;
		};

		hsls_25m_div2_clk: hsls_25m_div2_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&hsls_25m_clk>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		sdio0_clk: sdio0_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
			clock-div = <1>;
			clock-mult = <1>;
		};

		sdio1_clk: sdio1_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
			clock-div = <1>;
			clock-mult = <1>;
		};