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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 | /* * Device Tree Source for UniPhier Pro5 SoC * * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ / { compatible = "socionext,uniphier-pro5"; #address-cells = <1>; #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; clocks = <&sys_clk 32>; enable-method = "psci"; next-level-cache = <&l2>; operating-points-v2 = <&cpu_opp>; }; }; cpu_opp: opp_table { compatible = "operating-points-v2"; opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; clock-latency-ns = <300>; }; opp-116667000 { opp-hz = /bits/ 64 <116667000>; clock-latency-ns = <300>; }; opp-150000000 { opp-hz = /bits/ 64 <150000000>; clock-latency-ns = <300>; }; opp-175000000 { opp-hz = /bits/ 64 <175000000>; clock-latency-ns = <300>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; clock-latency-ns = <300>; }; opp-233334000 { opp-hz = /bits/ 64 <233334000>; clock-latency-ns = <300>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; clock-latency-ns = <300>; }; opp-350000000 { opp-hz = /bits/ 64 <350000000>; clock-latency-ns = <300>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; clock-latency-ns = <300>; }; opp-466667000 { opp-hz = /bits/ 64 <466667000>; clock-latency-ns = <300>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; clock-latency-ns = <300>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; clock-latency-ns = <300>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; clock-latency-ns = <300>; }; opp-933334000 { opp-hz = /bits/ 64 <933334000>; clock-latency-ns = <300>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; clock-latency-ns = <300>; }; opp-1400000000 { opp-hz = /bits/ 64 <1400000000>; clock-latency-ns = <300>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clocks { refclk: ref { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; arm_timer_clk: arm_timer_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <50000000>; }; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; interrupt-parent = <&intc>; l2: l2-cache@500c0000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; interrupts = <0 190 4>, <0 191 4>; cache-unified; cache-size = <(2 * 1024 * 1024)>; cache-sets = <512>; cache-line-size = <128>; cache-level = <2>; next-level-cache = <&l3>; }; l3: l3-cache@500c8000 { compatible = "socionext,uniphier-system-cache"; reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; interrupts = <0 174 4>, <0 175 4>; cache-unified; cache-size = <(2 * 1024 * 1024)>; cache-sets = <512>; cache-line-size = <256>; cache-level = <3>; }; serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006800 0x40>; interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; clocks = <&peri_clk 0>; }; serial1: serial@54006900 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006900 0x40>; interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006a00 0x40>; interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { compatible = "socionext,uniphier-uart"; status = "disabled"; reg = <0x54006b00 0x40>; interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; clocks = <&peri_clk 3>; }; i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58780000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clocks = <&peri_clk 4>; clock-frequency = <100000>; }; i2c1: i2c@58781000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58781000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; clocks = <&peri_clk 5>; clock-frequency = <100000>; }; i2c2: i2c@58782000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58782000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 43 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clocks = <&peri_clk 6>; clock-frequency = <100000>; }; i2c3: i2c@58783000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; reg = <0x58783000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; clocks = <&peri_clk 7>; clock-frequency = <100000>; }; /* i2c4 does not exist */ /* chip-internal connection for DMD */ i2c5: i2c@58785000 { compatible = "socionext,uniphier-fi2c"; reg = <0x58785000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; clocks = <&peri_clk 9>; clock-frequency = <400000>; }; /* chip-internal connection for HDMI */ i2c6: i2c@58786000 { compatible = "socionext,uniphier-fi2c"; reg = <0x58786000 0x80>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; clocks = <&peri_clk 10>; clock-frequency = <400000>; }; system_bus: system-bus@58c00000 { compatible = "socionext,uniphier-system-bus"; status = "disabled"; reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_system_bus>; }; smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; sdctrl@59810000 { compatible = "socionext,uniphier-pro5-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x400>; sd_clk: clock { compatible = "socionext,uniphier-pro5-sd-clock"; #clock-cells = <1>; }; sd_rst: reset { compatible = "socionext,uniphier-pro5-sd-reset"; #reset-cells = <1>; }; }; perictrl@59820000 { compatible = "socionext,uniphier-pro5-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; peri_clk: clock { compatible = "socionext,uniphier-pro5-peri-clock"; #clock-cells = <1>; }; peri_rst: reset { compatible = "socionext,uniphier-pro5-peri-reset"; #reset-cells = <1>; }; }; soc-glue@5f800000 { compatible = "socionext,uniphier-pro5-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; pinctrl: pinctrl { compatible = "socionext,uniphier-pro5-pinctrl"; }; }; aidet: aidet@5fc20000 { compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; interrupt-controller; #interrupt-cells = <2>; }; timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; interrupts = <1 11 0x304>; clocks = <&arm_timer_clk>; }; timer@60000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x60000600 0x20>; interrupts = <1 13 0x304>; clocks = <&arm_timer_clk>; }; intc: interrupt-controller@60001000 { compatible = "arm,cortex-a9-gic"; reg = <0x60001000 0x1000>, <0x60000100 0x100>; #interrupt-cells = <3>; interrupt-controller; }; sysctrl@61840000 { compatible = "socionext,uniphier-pro5-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-pro5-clock"; #clock-cells = <1>; }; sys_rst: reset { compatible = "socionext,uniphier-pro5-reset"; #reset-cells = <1>; }; }; nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; interrupts = <0 65 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand2cs>; clocks = <&sys_clk 2>; }; }; }; #include "uniphier-pinctrl.dtsi" |