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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 | /* * T1040/T1042 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; /include/ "e5500_power_isa.dtsi" / { #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; aliases { ccsr = &soc; dcsr = &dcsr; serial0 = &serial0; serial1 = &serial1; serial2 = &serial2; serial3 = &serial3; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; pci3 = &pci3; usb0 = &usb0; usb1 = &usb1; sdhc = &sdhc; crypto = &crypto; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: PowerPC,e5500@0 { device_type = "cpu"; reg = <0>; clocks = <&mux0>; next-level-cache = <&L2_1>; L2_1: l2-cache { next-level-cache = <&cpc>; }; }; cpu1: PowerPC,e5500@1 { device_type = "cpu"; reg = <1>; clocks = <&mux1>; next-level-cache = <&L2_2>; L2_2: l2-cache { next-level-cache = <&cpc>; }; }; cpu2: PowerPC,e5500@2 { device_type = "cpu"; reg = <2>; clocks = <&mux2>; next-level-cache = <&L2_3>; L2_3: l2-cache { next-level-cache = <&cpc>; }; }; cpu3: PowerPC,e5500@3 { device_type = "cpu"; reg = <3>; clocks = <&mux3>; next-level-cache = <&L2_4>; L2_4: l2-cache { next-level-cache = <&cpc>; }; }; }; }; |