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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 | /* * intc-2.c * * General interrupt controller code for the many ColdFire cores that use * interrupt controllers with 63 interrupt sources, organized as 56 fully- * programmable + 7 fixed-level interrupt sources. This includes the 523x * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such * controllers, and the 547x and 548x families which have only one of them. * * The external 7 fixed interrupts are part the the Edge Port unit of these * ColdFire parts. They can be configured as level or edge triggered. * * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive * for more details. */ #include <linux/types.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> #include <asm/coldfire.h> #include <asm/mcfsim.h> #include <asm/traps.h> /* * Bit definitions for the ICR family of registers. */ #define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */ #define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */ /* * The EDGE Port interrupts are the fixed 7 external interrupts. * They need some special treatment, for example they need to be acked. */ #define EINT0 64 /* Is not actually used, but spot reserved for it */ #define EINT1 65 /* EDGE Port interrupt 1 */ #define EINT7 71 /* EDGE Port interrupt 7 */ #ifdef MCFICM_INTC1 #define NR_VECS 128 #else #define NR_VECS 64 #endif static void intc_irq_mask(struct irq_data *d) { unsigned int irq = d->irq - MCFINT_VECBASE; unsigned long imraddr; u32 val, imrbit; #ifdef MCFICM_INTC1 imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; #else imraddr = MCFICM_INTC0; #endif imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; imrbit = 0x1 << (irq & 0x1f); val = __raw_readl(imraddr); __raw_writel(val | imrbit, imraddr); } static void intc_irq_unmask(struct irq_data *d) { unsigned int irq = d->irq - MCFINT_VECBASE; unsigned long imraddr; u32 val, imrbit; #ifdef MCFICM_INTC1 imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; #else imraddr = MCFICM_INTC0; #endif imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); imrbit = 0x1 << (irq & 0x1f); /* Don't set the "maskall" bit! */ if ((irq & 0x20) == 0) imrbit |= 0x1; val = __raw_readl(imraddr); __raw_writel(val & ~imrbit, imraddr); } /* * Only the external (or EDGE Port) interrupts need to be acknowledged * here, as part of the IRQ handler. They only really need to be ack'ed * if they are in edge triggered mode, but there is no harm in doing it * for all types. */ static void intc_irq_ack(struct irq_data *d) { unsigned int irq = d->irq; __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR); } /* * Each vector needs a unique priority and level associated with it. * We don't really care so much what they are, we don't rely on the * traditional priority interrupt scheme of the m68k/ColdFire. This * only needs to be set once for an interrupt, and we will never change * these values once we have set them. */ static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6); static unsigned int intc_irq_startup(struct irq_data *d) { unsigned int irq = d->irq - MCFINT_VECBASE; unsigned long icraddr; #ifdef MCFICM_INTC1 icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; #else icraddr = MCFICM_INTC0; #endif icraddr += MCFINTC_ICR0 + (irq & 0x3f); if (__raw_readb(icraddr) == 0) __raw_writeb(intc_intpri--, icraddr); irq = d->irq; if ((irq >= EINT1) && (irq <= EINT7)) { u8 v; irq -= EINT0; /* Set EPORT line as input */ v = __raw_readb(MCFEPORT_EPDDR); __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR); /* Set EPORT line as interrupt source */ v = __raw_readb(MCFEPORT_EPIER); __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER); } intc_irq_unmask(d); return 0; } static int intc_irq_set_type(struct irq_data *d, unsigned int type) { unsigned int irq = d->irq; u16 pa, tb; switch (type) { case IRQ_TYPE_EDGE_RISING: tb = 0x1; break; case IRQ_TYPE_EDGE_FALLING: tb = 0x2; break; case IRQ_TYPE_EDGE_BOTH: tb = 0x3; break; default: /* Level triggered */ tb = 0; break; } if (tb) irq_set_handler(irq, handle_edge_irq); irq -= EINT0; pa = __raw_readw(MCFEPORT_EPPAR); pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2)); __raw_writew(pa, MCFEPORT_EPPAR); return 0; } static struct irq_chip intc_irq_chip = { .name = "CF-INTC", .irq_startup = intc_irq_startup, .irq_mask = intc_irq_mask, .irq_unmask = intc_irq_unmask, }; static struct irq_chip intc_irq_chip_edge_port = { .name = "CF-INTC-EP", .irq_startup = intc_irq_startup, .irq_mask = intc_irq_mask, .irq_unmask = intc_irq_unmask, .irq_ack = intc_irq_ack, .irq_set_type = intc_irq_set_type, }; void __init init_IRQ(void) { int irq; /* Mask all interrupt sources */ __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL); #ifdef MCFICM_INTC1 __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL); #endif for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { if ((irq >= EINT1) && (irq <=EINT7)) irq_set_chip(irq, &intc_irq_chip_edge_port); else irq_set_chip(irq, &intc_irq_chip); irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); irq_set_handler(irq, handle_level_irq); } } |