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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 | /* * arch/xtensa/kernel/head.S * * Xtensa Processor startup code. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2008 Tensilica Inc. * * Chris Zankel <chris@zankel.net> * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca> * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> * Kevin Chea */ #include <asm/processor.h> #include <asm/page.h> #include <asm/cacheasm.h> #include <asm/initialize_mmu.h> #include <asm/mxregs.h> #include <linux/init.h> #include <linux/linkage.h> /* * This module contains the entry code for kernel images. It performs the * minimal setup needed to call the generic C routines. * * Prerequisites: * * - The kernel image has been loaded to the actual address where it was * compiled to. * - a2 contains either 0 or a pointer to a list of boot parameters. * (see setup.c for more details) * */ /* * _start * * The bootloader passes a pointer to a list of boot parameters in a2. */ /* The first bytes of the kernel image must be an instruction, so we * manually allocate and define the literal constant we need for a jx * instruction. */ __HEAD .begin no-absolute-literals ENTRY(_start) /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ wsr a2, excsave1 _j _SetupOCD .align 4 .literal_position .Lstartup: .word _startup .align 4 _SetupOCD: /* * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions). * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow * xt-gdb to single step via DEBUG exceptions received directly * by ocd. */ movi a1, 1 movi a0, 0 wsr a1, windowstart wsr a0, windowbase rsync movi a1, LOCKLEVEL wsr a1, ps rsync .global _SetupMMU _SetupMMU: Offset = _SetupMMU - _start #ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX initialize_mmu #if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY rsr a2, excsave1 movi a3, 0x08000000 bgeu a2, a3, 1f movi a3, 0xd0000000 add a2, a2, a3 wsr a2, excsave1 1: #endif #endif .end no-absolute-literals l32r a0, .Lstartup jx a0 ENDPROC(_start) __REF .literal_position ENTRY(_startup) /* Set a0 to 0 for the remaining initialization. */ movi a0, 0 #if XCHAL_HAVE_VECBASE movi a2, VECBASE_RESET_VADDR wsr a2, vecbase #endif /* Clear debugging registers. */ #if XCHAL_HAVE_DEBUG #if XCHAL_NUM_IBREAK > 0 wsr a0, ibreakenable #endif wsr a0, icount movi a1, 15 wsr a0, icountlevel .set _index, 0 .rept XCHAL_NUM_DBREAK - 1 wsr a0, SREG_DBREAKC + _index .set _index, _index + 1 .endr #endif /* Clear CCOUNT (not really necessary, but nice) */ wsr a0, ccount # not really necessary, but nice /* Disable zero-loops. */ #if XCHAL_HAVE_LOOPS wsr a0, lcount #endif /* Disable all timers. */ .set _index, 0 .rept XCHAL_NUM_TIMERS wsr a0, SREG_CCOMPARE + _index .set _index, _index + 1 .endr /* Interrupt initialization. */ movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE wsr a0, intenable wsr a2, intclear /* Disable coprocessors. */ #if XCHAL_HAVE_CP wsr a0, cpenable #endif /* Initialize the caches. * a2, a3 are just working registers (clobbered). */ #if XCHAL_DCACHE_LINE_LOCKABLE ___unlock_dcache_all a2 a3 #endif #if XCHAL_ICACHE_LINE_LOCKABLE ___unlock_icache_all a2 a3 #endif ___invalidate_dcache_all a2 a3 ___invalidate_icache_all a2 a3 isync #ifdef CONFIG_HAVE_SMP movi a2, CCON # MX External Register to Configure Cache movi a3, 1 wer a3, a2 #endif /* Setup stack and enable window exceptions (keep irqs disabled) */ movi a1, start_info l32i a1, a1, 0 movi a2, (1 << PS_WOE_BIT) | LOCKLEVEL # WOE=1, INTLEVEL=LOCKLEVEL, UM=0 wsr a2, ps # (enable reg-windows; progmode stack) rsync /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/ movi a2, debug_exception wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL #ifdef CONFIG_SMP /* * Notice that we assume with SMP that cores have PRID * supported by the cores. */ rsr a2, prid bnez a2, .Lboot_secondary #endif /* CONFIG_SMP */ /* Unpack data sections * * The linker script used to build the Linux kernel image * creates a table located at __boot_reloc_table_start * that contans the information what data needs to be unpacked. * * Uses a2-a7. */ movi a2, __boot_reloc_table_start movi a3, __boot_reloc_table_end 1: beq a2, a3, 3f # no more entries? l32i a4, a2, 0 # start destination (in RAM) l32i a5, a2, 4 # end desination (in RAM) l32i a6, a2, 8 # start source (in ROM) addi a2, a2, 12 # next entry beq a4, a5, 1b # skip, empty entry beq a4, a6, 1b # skip, source and dest. are the same 2: l32i a7, a6, 0 # load word addi a6, a6, 4 s32i a7, a4, 0 # store word addi a4, a4, 4 bltu a4, a5, 2b j 1b 3: /* All code and initialized data segments have been copied. * Now clear the BSS segment. */ movi a2, __bss_start # start of BSS movi a3, __bss_stop # end of BSS __loopt a2, a3, a4, 2 s32i a0, a2, 0 __endla a2, a4, 4 #if XCHAL_DCACHE_IS_WRITEBACK /* After unpacking, flush the writeback cache to memory so the * instructions/data are available. */ ___flush_dcache_all a2 a3 #endif memw isync ___invalidate_icache_all a2 a3 isync movi a6, 0 xsr a6, excsave1 /* init_arch kick-starts the linux kernel */ movi a4, init_arch callx4 a4 movi a4, start_kernel callx4 a4 should_never_return: j should_never_return #ifdef CONFIG_SMP .Lboot_secondary: movi a2, cpu_start_ccount 1: l32i a3, a2, 0 beqi a3, 0, 1b movi a3, 0 s32i a3, a2, 0 memw 1: l32i a3, a2, 0 beqi a3, 0, 1b wsr a3, ccount movi a3, 0 s32i a3, a2, 0 memw movi a6, 0 wsr a6, excsave1 movi a4, secondary_start_kernel callx4 a4 j should_never_return #endif /* CONFIG_SMP */ ENDPROC(_startup) #ifdef CONFIG_HOTPLUG_CPU ENTRY(cpu_restart) #if XCHAL_DCACHE_IS_WRITEBACK ___flush_invalidate_dcache_all a2 a3 #else ___invalidate_dcache_all a2 a3 #endif memw movi a2, CCON # MX External Register to Configure Cache movi a3, 0 wer a3, a2 extw rsr a0, prid neg a2, a0 movi a3, cpu_start_id s32i a2, a3, 0 #if XCHAL_DCACHE_IS_WRITEBACK dhwbi a3, 0 #endif 1: l32i a2, a3, 0 dhi a3, 0 bne a2, a0, 1b /* * Initialize WB, WS, and clear PS.EXCM (to allow loop instructions). * Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow * xt-gdb to single step via DEBUG exceptions received directly * by ocd. */ movi a1, 1 movi a0, 0 wsr a1, windowstart wsr a0, windowbase rsync movi a1, LOCKLEVEL wsr a1, ps rsync j _startup ENDPROC(cpu_restart) #endif /* CONFIG_HOTPLUG_CPU */ /* * DATA section */ .section ".data.init.refok" .align 4 ENTRY(start_info) .long init_thread_union + KERNEL_STACK_SIZE /* * BSS section */ __PAGE_ALIGNED_BSS #ifdef CONFIG_MMU ENTRY(swapper_pg_dir) .fill PAGE_SIZE, 1, 0 END(swapper_pg_dir) #endif ENTRY(empty_zero_page) .fill PAGE_SIZE, 1, 0 END(empty_zero_page) |