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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 | /* * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. * All rights reserved * www.brocade.com * * Linux driver for Brocade Fibre Channel Host Bus Adapter. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License (GPL) Version 2 as * published by the Free Software Foundation * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. */ #include "bfad_drv.h" #include "bfa_modules.h" #include "bfi_reg.h" BFA_TRC_FILE(HAL, IOCFC_CT); /* * Dummy interrupt handler for handling spurious interrupt during chip-reinit. */ static void bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec) { } void bfa_hwct_reginit(struct bfa_s *bfa) { struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); int fn = bfa_ioc_pcifn(&bfa->ioc); if (fn == 0) { bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK); } else { bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); } } void bfa_hwct2_reginit(struct bfa_s *bfa) { struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS); bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK); } void bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq) { u32 r32; r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]); writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]); } /* * Actions to respond RME Interrupt for Catapult ASIC: * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx()) * - Acknowledge by writing to RME Queue Control register * - Update CI */ void bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) { u32 r32; r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]); bfa_rspq_ci(bfa, rspq) = ci; writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); mmiowb(); } /* * Actions to respond RME Interrupt for Catapult2 ASIC: * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx()) * - Update CI */ void bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) { bfa_rspq_ci(bfa, rspq) = ci; writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); mmiowb(); } void bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, u32 *num_vecs, u32 *max_vec_bit) { *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1; *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1)); *num_vecs = BFI_MSIX_CT_MAX; } /* * Setup MSI-X vector for catapult */ void bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs) { WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX)); bfa_trc(bfa, nvecs); bfa->msix.nvecs = nvecs; bfa_hwct_msix_uninstall(bfa); } void bfa_hwct_msix_ctrl_install(struct bfa_s *bfa) { if (bfa->msix.nvecs == 0) return; if (bfa->msix.nvecs == 1) bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all; else bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err; } void bfa_hwct_msix_queue_install(struct bfa_s *bfa) { int i; if (bfa->msix.nvecs == 0) return; if (bfa->msix.nvecs == 1) { for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++) bfa->msix.handler[i] = bfa_msix_all; return; } for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++) bfa->msix.handler[i] = bfa_msix_reqq; for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++) bfa->msix.handler[i] = bfa_msix_rspq; } void bfa_hwct_msix_uninstall(struct bfa_s *bfa) { int i; for (i = 0; i < BFI_MSIX_CT_MAX; i++) bfa->msix.handler[i] = bfa_hwct_msix_dummy; } /* * Enable MSI-X vectors */ void bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) { bfa_trc(bfa, 0); bfa_ioc_isr_mode_set(&bfa->ioc, msix); } void bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) { *start = BFI_MSIX_RME_QMIN_CT; *end = BFI_MSIX_RME_QMAX_CT; } |