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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 | /* * MPC8541 CDS Device Tree Source * * Copyright 2006, 2008 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ /dts-v1/; /include/ "fsl/e500v2_power_isa.dtsi" / { model = "MPC8541CDS"; compatible = "MPC8541CDS", "MPC85xxCDS"; #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &enet0; ethernet1 = &enet1; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8541@0 { device_type = "cpu"; reg = <0x0>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <0x8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot next-level-cache = <&L2>; }; }; memory { device_type = "memory"; reg = <0x0 0x8000000>; // 128M at 0x0 }; soc8541@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; bus-frequency = <0>; ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <8>; }; ecm@1000 { compatible = "fsl,mpc8541-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; memory-controller@2000 { compatible = "fsl,mpc8541-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; L2: l2-cache-controller@20000 { compatible = "fsl,mpc8541-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x40000>; // L2, 256K interrupt-parent = <&mpic>; interrupts = <16 2>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; dma@21300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8541-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8541-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8541-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8541-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <23 2>; }; }; enet0: ethernet@24000 { #address-cells = <1>; #size-cells = <1>; cell-index = <0>; device_type = "network"; model = "TSEC"; compatible = "gianfar"; reg = <0x24000 0x1000>; ranges = <0x0 0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <29 2 30 2 34 2>; interrupt-parent = <&mpic>; tbi-handle = <&tbi0>; phy-handle = <&phy0>; mdio@520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; reg = <0x520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <5 1>; reg = <0x0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; interrupts = <5 1>; reg = <0x1>; device_type = "ethernet-phy"; }; tbi0: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; enet1: ethernet@25000 { #address-cells = <1>; #size-cells = <1>; cell-index = <1>; device_type = "network"; model = "TSEC"; compatible = "gianfar"; reg = <0x25000 0x1000>; ranges = <0x0 0x25000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <35 2 36 2 40 2>; interrupt-parent = <&mpic>; tbi-handle = <&tbi1>; phy-handle = <&phy1>; mdio@520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-tbi"; reg = <0x520 0x20>; tbi1: tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "fsl,ns16550", "ns16550"; reg = <0x4500 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? interrupts = <42 2>; interrupt-parent = <&mpic>; }; serial1: serial@4600 { cell-index = <1>; device_type = "serial"; compatible = "fsl,ns16550", "ns16550"; reg = <0x4600 0x100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? interrupts = <42 2>; interrupt-parent = <&mpic>; }; crypto@30000 { compatible = "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <45 2>; interrupt-parent = <&mpic>; fsl,num-channels = <4>; fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0x7e>; fsl,descriptor-types-mask = <0x01010ebf>; }; mpic: pic@40000 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; }; cpm@919c0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; reg = <0x919c0 0x30>; ranges; muram@80000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x80000 0x10000>; data@0 { compatible = "fsl,cpm-muram-data"; reg = <0x0 0x2000 0x9000 0x1000>; }; }; brg@919f0 { compatible = "fsl,mpc8541-brg", "fsl,cpm2-brg", "fsl,cpm-brg"; reg = <0x919f0 0x10 0x915f0 0x10>; }; cpmpic: pic@90c00 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; interrupts = <46 2>; interrupt-parent = <&mpic>; reg = <0x90c00 0x80>; compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; }; }; }; pci0: pci@e0008000 { interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x10 */ 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x11 */ 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x12 (Slot 1) */ 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 /* IDSEL 0x13 (Slot 2) */ 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 /* IDSEL 0x14 (Slot 3) */ 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 /* IDSEL 0x15 (Slot 4) */ 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 /* Bus 1 (Tundra Bridge) */ /* IDSEL 0x12 (ISA bridge) */ 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; interrupts = <24 2>; bus-range = <0 0>; ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0xe0008000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; i8259@19000 { interrupt-controller; device_type = "interrupt-controller"; reg = <0x19000 0x0 0x0 0x0 0x1>; #address-cells = <0>; #interrupt-cells = <2>; compatible = "chrp,iic"; interrupts = <1>; interrupt-parent = <&pci0>; }; }; pci1: pci@e0009000 { interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x15 */ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; interrupt-parent = <&mpic>; interrupts = <25 2>; bus-range = <0 0>; ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; clock-frequency = <66666666>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0xe0009000 0x1000>; compatible = "fsl,mpc8540-pci"; device_type = "pci"; }; }; |