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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 | /* * Atheros AR71XX/AR724X/AR913X common routines * * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> #include <linux/err.h> #include <linux/clk.h> #include <asm/mach-ath79/ath79.h> #include <asm/mach-ath79/ar71xx_regs.h> #include "common.h" #define AR71XX_BASE_FREQ 40000000 #define AR724X_BASE_FREQ 5000000 #define AR913X_BASE_FREQ 5000000 struct clk { unsigned long rate; }; static struct clk ath79_ref_clk; static struct clk ath79_cpu_clk; static struct clk ath79_ddr_clk; static struct clk ath79_ahb_clk; static struct clk ath79_wdt_clk; static struct clk ath79_uart_clk; static void __init ar71xx_clocks_init(void) { u32 pll; u32 freq; u32 div; ath79_ref_clk.rate = AR71XX_BASE_FREQ; pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; freq = div * ath79_ref_clk.rate; div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; ath79_cpu_clk.rate = freq / div; div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; ath79_ddr_clk.rate = freq / div; div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; ath79_wdt_clk.rate = ath79_ahb_clk.rate; ath79_uart_clk.rate = ath79_ahb_clk.rate; } static void __init ar724x_clocks_init(void) { u32 pll; u32 freq; u32 div; ath79_ref_clk.rate = AR724X_BASE_FREQ; pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); freq = div * ath79_ref_clk.rate; div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); freq *= div; ath79_cpu_clk.rate = freq; div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; ath79_ddr_clk.rate = freq / div; div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; ath79_wdt_clk.rate = ath79_ahb_clk.rate; ath79_uart_clk.rate = ath79_ahb_clk.rate; } static void __init ar913x_clocks_init(void) { u32 pll; u32 freq; u32 div; ath79_ref_clk.rate = AR913X_BASE_FREQ; pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG); div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK); freq = div * ath79_ref_clk.rate; ath79_cpu_clk.rate = freq; div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1; ath79_ddr_clk.rate = freq / div; div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2; ath79_ahb_clk.rate = ath79_cpu_clk.rate / div; ath79_wdt_clk.rate = ath79_ahb_clk.rate; ath79_uart_clk.rate = ath79_ahb_clk.rate; } void __init ath79_clocks_init(void) { if (soc_is_ar71xx()) ar71xx_clocks_init(); else if (soc_is_ar724x()) ar724x_clocks_init(); else if (soc_is_ar913x()) ar913x_clocks_init(); else BUG(); pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, " "Ref:%lu.%03luMHz", ath79_cpu_clk.rate / 1000000, (ath79_cpu_clk.rate / 1000) % 1000, ath79_ddr_clk.rate / 1000000, (ath79_ddr_clk.rate / 1000) % 1000, ath79_ahb_clk.rate / 1000000, (ath79_ahb_clk.rate / 1000) % 1000, ath79_ref_clk.rate / 1000000, (ath79_ref_clk.rate / 1000) % 1000); } /* * Linux clock API */ struct clk *clk_get(struct device *dev, const char *id) { if (!strcmp(id, "ref")) return &ath79_ref_clk; if (!strcmp(id, "cpu")) return &ath79_cpu_clk; if (!strcmp(id, "ddr")) return &ath79_ddr_clk; if (!strcmp(id, "ahb")) return &ath79_ahb_clk; if (!strcmp(id, "wdt")) return &ath79_wdt_clk; if (!strcmp(id, "uart")) return &ath79_uart_clk; return ERR_PTR(-ENOENT); } EXPORT_SYMBOL(clk_get); int clk_enable(struct clk *clk) { return 0; } EXPORT_SYMBOL(clk_enable); void clk_disable(struct clk *clk) { } EXPORT_SYMBOL(clk_disable); unsigned long clk_get_rate(struct clk *clk) { return clk->rate; } EXPORT_SYMBOL(clk_get_rate); void clk_put(struct clk *clk) { } EXPORT_SYMBOL(clk_put); |