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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 | /* * Copyright (C) 2013 STMicroelectronics (R&D) Limited. * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. */ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> / { L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xfffe2000 0x1000>; arm,data-latency = <3 2 2>; arm,tag-latency = <1 1 1>; cache-unified; cache-level = <2>; }; soc { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; compatible = "simple-bus"; syscfg_sbc: sbc-syscfg@fe600000{ compatible = "st,stih415-sbc-syscfg", "syscon"; reg = <0xfe600000 0xb4>; }; syscfg_front: front-syscfg@fee10000{ compatible = "st,stih415-front-syscfg", "syscon"; reg = <0xfee10000 0x194>; }; syscfg_rear: rear-syscfg@fe830000{ compatible = "st,stih415-rear-syscfg", "syscon"; reg = <0xfe830000 0x190>; }; /* MPE syscfgs */ syscfg_left: left-syscfg@fd690000{ compatible = "st,stih415-left-syscfg", "syscon"; reg = <0xfd690000 0x78>; }; syscfg_right: right-syscfg@fd320000{ compatible = "st,stih415-right-syscfg", "syscon"; reg = <0xfd320000 0x180>; }; syscfg_system: system-syscfg@fdde0000 { compatible = "st,stih415-system-syscfg", "syscon"; reg = <0xfdde0000 0x15c>; }; syscfg_lpm: lpm-syscfg@fe4b5100{ compatible = "st,stih415-lpm-syscfg", "syscon"; reg = <0xfe4b5100 0x08>; }; serial2: serial@fed32000 { compatible = "st,asc"; status = "disabled"; reg = <0xfed32000 0x2c>; interrupts = <0 197 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; clocks = <&CLKS_ICN_REG_0>; }; /* SBC comms block ASCs in SASG1 */ sbc_serial1: serial@fe531000 { compatible = "st,asc"; status = "disabled"; reg = <0xfe531000 0x2c>; interrupts = <0 210 0>; clocks = <&CLK_SYSIN>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; i2c@fed40000 { compatible = "st,comms-ssc4-i2c"; reg = <0xfed40000 0x110>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CLKS_ICN_REG_0>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; status = "disabled"; }; i2c@fed41000 { compatible = "st,comms-ssc4-i2c"; reg = <0xfed41000 0x110>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CLKS_ICN_REG_0>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1_default>; status = "disabled"; }; i2c@fe540000 { compatible = "st,comms-ssc4-i2c"; reg = <0xfe540000 0x110>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CLK_SYSIN>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_i2c0_default>; status = "disabled"; }; i2c@fe541000 { compatible = "st,comms-ssc4-i2c"; reg = <0xfe541000 0x110>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CLK_SYSIN>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_i2c1_default>; status = "disabled"; }; }; }; |