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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 | /* * Wondermedia I2C Master Mode Driver * * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> * * Derived from GPLv2+ licensed source: * - Copyright (C) 2008 WonderMedia Technologies, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2, or * (at your option) any later version. as published by the Free Software * Foundation */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #define REG_CR 0x00 #define REG_TCR 0x02 #define REG_CSR 0x04 #define REG_ISR 0x06 #define REG_IMR 0x08 #define REG_CDR 0x0A #define REG_TR 0x0C #define REG_MCR 0x0E #define REG_SLAVE_CR 0x10 #define REG_SLAVE_SR 0x12 #define REG_SLAVE_ISR 0x14 #define REG_SLAVE_IMR 0x16 #define REG_SLAVE_DR 0x18 #define REG_SLAVE_TR 0x1A /* REG_CR Bit fields */ #define CR_TX_NEXT_ACK 0x0000 #define CR_ENABLE 0x0001 #define CR_TX_NEXT_NO_ACK 0x0002 #define CR_TX_END 0x0004 #define CR_CPU_RDY 0x0008 #define SLAV_MODE_SEL 0x8000 /* REG_TCR Bit fields */ #define TCR_STANDARD_MODE 0x0000 #define TCR_MASTER_WRITE 0x0000 #define TCR_HS_MODE 0x2000 #define TCR_MASTER_READ 0x4000 #define TCR_FAST_MODE 0x8000 #define TCR_SLAVE_ADDR_MASK 0x007F /* REG_ISR Bit fields */ #define ISR_NACK_ADDR 0x0001 #define ISR_BYTE_END 0x0002 #define ISR_SCL_TIMEOUT 0x0004 #define ISR_WRITE_ALL 0x0007 /* REG_IMR Bit fields */ #define IMR_ENABLE_ALL 0x0007 /* REG_CSR Bit fields */ #define CSR_RCV_NOT_ACK 0x0001 #define CSR_RCV_ACK_MASK 0x0001 #define CSR_READY_MASK 0x0002 /* REG_TR */ #define SCL_TIMEOUT(x) (((x) & 0xFF) << 8) #define TR_STD 0x0064 #define TR_HS 0x0019 /* REG_MCR */ #define MCR_APB_96M 7 #define MCR_APB_166M 12 #define I2C_MODE_STANDARD 0 #define I2C_MODE_FAST 1 #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000)) struct wmt_i2c_dev { struct i2c_adapter adapter; struct completion complete; struct device *dev; void __iomem *base; struct clk *clk; int mode; int irq; u16 cmd_status; }; static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev) { unsigned long timeout; timeout = jiffies + WMT_I2C_TIMEOUT; while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { if (time_after(jiffies, timeout)) { dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n"); return -EBUSY; } msleep(20); } return 0; } static int wmt_check_status(struct wmt_i2c_dev *i2c_dev) { int ret = 0; if (i2c_dev->cmd_status & ISR_NACK_ADDR) ret = -EIO; if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT) ret = -ETIMEDOUT; return ret; } static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg, int last) { struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); u16 val, tcr_val; int ret, wait_result; int xfer_len = 0; if (!(pmsg->flags & I2C_M_NOSTART)) { ret = wmt_i2c_wait_bus_not_busy(i2c_dev); if (ret < 0) return ret; } if (pmsg->len == 0) { /* * We still need to run through the while (..) once, so * start at -1 and break out early from the loop */ xfer_len = -1; writew(0, i2c_dev->base + REG_CDR); } else { writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); } if (!(pmsg->flags & I2C_M_NOSTART)) { val = readw(i2c_dev->base + REG_CR); val &= ~CR_TX_END; writew(val, i2c_dev->base + REG_CR); val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } reinit_completion(&i2c_dev->complete); if (i2c_dev->mode == I2C_MODE_STANDARD) tcr_val = TCR_STANDARD_MODE; else tcr_val = TCR_FAST_MODE; tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK)); writew(tcr_val, i2c_dev->base + REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } while (xfer_len < pmsg->len) { wait_result = wait_for_completion_timeout(&i2c_dev->complete, 500 * HZ / 1000); if (wait_result == 0) return -ETIMEDOUT; ret = wmt_check_status(i2c_dev); if (ret) return ret; xfer_len++; val = readw(i2c_dev->base + REG_CSR); if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) { dev_dbg(i2c_dev->dev, "write RCV NACK error\n"); return -EIO; } if (pmsg->len == 0) { val = CR_TX_END | CR_CPU_RDY | CR_ENABLE; writew(val, i2c_dev->base + REG_CR); break; } if (xfer_len == pmsg->len) { if (last != 1) writew(CR_ENABLE, i2c_dev->base + REG_CR); } else { writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + REG_CDR); writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); } } return 0; } static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg, int last) { struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); u16 val, tcr_val; int ret, wait_result; u32 xfer_len = 0; if (!(pmsg->flags & I2C_M_NOSTART)) { ret = wmt_i2c_wait_bus_not_busy(i2c_dev); if (ret < 0) return ret; } val = readw(i2c_dev->base + REG_CR); val &= ~CR_TX_END; writew(val, i2c_dev->base + REG_CR); val = readw(i2c_dev->base + REG_CR); val &= ~CR_TX_NEXT_NO_ACK; writew(val, i2c_dev->base + REG_CR); if (!(pmsg->flags & I2C_M_NOSTART)) { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } if (pmsg->len == 1) { val = readw(i2c_dev->base + REG_CR); val |= CR_TX_NEXT_NO_ACK; writew(val, i2c_dev->base + REG_CR); } reinit_completion(&i2c_dev->complete); if (i2c_dev->mode == I2C_MODE_STANDARD) tcr_val = TCR_STANDARD_MODE; else tcr_val = TCR_FAST_MODE; tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK); writew(tcr_val, i2c_dev->base + REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } while (xfer_len < pmsg->len) { wait_result = wait_for_completion_timeout(&i2c_dev->complete, 500 * HZ / 1000); if (!wait_result) return -ETIMEDOUT; ret = wmt_check_status(i2c_dev); if (ret) return ret; pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; xfer_len++; if (xfer_len == pmsg->len - 1) { val = readw(i2c_dev->base + REG_CR); val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY); writew(val, i2c_dev->base + REG_CR); } else { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } } return 0; } static int wmt_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct i2c_msg *pmsg; int i, is_last; int ret = 0; for (i = 0; ret >= 0 && i < num; i++) { is_last = ((i + 1) == num); pmsg = &msgs[i]; if (pmsg->flags & I2C_M_RD) ret = wmt_i2c_read(adap, pmsg, is_last); else ret = wmt_i2c_write(adap, pmsg, is_last); } return (ret < 0) ? ret : i; } static u32 wmt_i2c_func(struct i2c_adapter *adap) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART; } static const struct i2c_algorithm wmt_i2c_algo = { .master_xfer = wmt_i2c_xfer, .functionality = wmt_i2c_func, }; static irqreturn_t wmt_i2c_isr(int irq, void *data) { struct wmt_i2c_dev *i2c_dev = data; /* save the status and write-clear it */ i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR); writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR); complete(&i2c_dev->complete); return IRQ_HANDLED; } static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev) { int err; err = clk_prepare_enable(i2c_dev->clk); if (err) { dev_err(i2c_dev->dev, "failed to enable clock\n"); return err; } err = clk_set_rate(i2c_dev->clk, 20000000); if (err) { dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n"); clk_disable_unprepare(i2c_dev->clk); return err; } writew(0, i2c_dev->base + REG_CR); writew(MCR_APB_166M, i2c_dev->base + REG_MCR); writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR); writew(CR_ENABLE, i2c_dev->base + REG_CR); readw(i2c_dev->base + REG_CSR); /* read clear */ writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); if (i2c_dev->mode == I2C_MODE_STANDARD) writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR); else writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR); return 0; } static int wmt_i2c_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct wmt_i2c_dev *i2c_dev; struct i2c_adapter *adap; struct resource *res; int err; u32 clk_rate; i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); if (!i2c_dev) { dev_err(&pdev->dev, "device memory allocation failed\n"); return -ENOMEM; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(i2c_dev->base)) return PTR_ERR(i2c_dev->base); i2c_dev->irq = irq_of_parse_and_map(np, 0); if (!i2c_dev->irq) { dev_err(&pdev->dev, "irq missing or invalid\n"); return -EINVAL; } i2c_dev->clk = of_clk_get(np, 0); if (IS_ERR(i2c_dev->clk)) { dev_err(&pdev->dev, "unable to request clock\n"); return PTR_ERR(i2c_dev->clk); } i2c_dev->mode = I2C_MODE_STANDARD; err = of_property_read_u32(np, "clock-frequency", &clk_rate); if ((!err) && (clk_rate == 400000)) i2c_dev->mode = I2C_MODE_FAST; i2c_dev->dev = &pdev->dev; err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0, "i2c", i2c_dev); if (err) { dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq); return err; } adap = &i2c_dev->adapter; i2c_set_adapdata(adap, i2c_dev); strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); adap->owner = THIS_MODULE; adap->algo = &wmt_i2c_algo; adap->dev.parent = &pdev->dev; adap->dev.of_node = pdev->dev.of_node; init_completion(&i2c_dev->complete); err = wmt_i2c_reset_hardware(i2c_dev); if (err) { dev_err(&pdev->dev, "error initializing hardware\n"); return err; } err = i2c_add_adapter(adap); if (err) { dev_err(&pdev->dev, "failed to add adapter\n"); return err; } platform_set_drvdata(pdev, i2c_dev); return 0; } static int wmt_i2c_remove(struct platform_device *pdev) { struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev); /* Disable interrupts, clock and delete adapter */ writew(0, i2c_dev->base + REG_IMR); clk_disable_unprepare(i2c_dev->clk); i2c_del_adapter(&i2c_dev->adapter); return 0; } static struct of_device_id wmt_i2c_dt_ids[] = { { .compatible = "wm,wm8505-i2c" }, { /* Sentinel */ }, }; static struct platform_driver wmt_i2c_driver = { .probe = wmt_i2c_probe, .remove = wmt_i2c_remove, .driver = { .name = "wmt-i2c", .owner = THIS_MODULE, .of_match_table = wmt_i2c_dt_ids, }, }; module_platform_driver(wmt_i2c_driver); MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter"); MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids); |