Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 | /* * Copyright (C) 2012 Texas Instruments * Author: Rob Clark <robdclark@gmail.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/module.h> #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> #include <drm/drm_encoder_slave.h> #include <drm/drm_edid.h> #include <drm/i2c/tda998x.h> #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) struct tda998x_priv { struct i2c_client *cec; uint16_t rev; uint8_t current_page; int dpms; bool is_hdmi_sink; u8 vip_cntrl_0; u8 vip_cntrl_1; u8 vip_cntrl_2; struct tda998x_encoder_params params; }; #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) /* The TDA9988 series of devices use a paged register scheme.. to simplify * things we encode the page # in upper bits of the register #. To read/ * write a given register, we need to make sure CURPAGE register is set * appropriately. Which implies reads/writes are not atomic. Fun! */ #define REG(page, addr) (((page) << 8) | (addr)) #define REG2ADDR(reg) ((reg) & 0xff) #define REG2PAGE(reg) (((reg) >> 8) & 0xff) #define REG_CURPAGE 0xff /* write */ /* Page 00h: General Control */ #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ # define MAIN_CNTRL0_SR (1 << 0) # define MAIN_CNTRL0_DECS (1 << 1) # define MAIN_CNTRL0_DEHS (1 << 2) # define MAIN_CNTRL0_CECS (1 << 3) # define MAIN_CNTRL0_CEHS (1 << 4) # define MAIN_CNTRL0_SCALER (1 << 7) #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ # define SOFTRESET_AUDIO (1 << 0) # define SOFTRESET_I2C_MASTER (1 << 1) #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ # define I2C_MASTER_DIS_MM (1 << 0) # define I2C_MASTER_DIS_FILT (1 << 1) # define I2C_MASTER_APP_STRT_LAT (1 << 2) #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ # define FEAT_POWERDOWN_SPDIF (1 << 3) #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ # define VIP_CNTRL_0_MIRR_A (1 << 7) # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) # define VIP_CNTRL_0_MIRR_B (1 << 3) # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ # define VIP_CNTRL_1_MIRR_C (1 << 7) # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) # define VIP_CNTRL_1_MIRR_D (1 << 3) # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ # define VIP_CNTRL_2_MIRR_E (1 << 7) # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) # define VIP_CNTRL_2_MIRR_F (1 << 3) # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ # define VIP_CNTRL_3_X_TGL (1 << 0) # define VIP_CNTRL_3_H_TGL (1 << 1) # define VIP_CNTRL_3_V_TGL (1 << 2) # define VIP_CNTRL_3_EMB (1 << 3) # define VIP_CNTRL_3_SYNC_DE (1 << 4) # define VIP_CNTRL_3_SYNC_HS (1 << 5) # define VIP_CNTRL_3_DE_INT (1 << 6) # define VIP_CNTRL_3_EDGE (1 << 7) #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) # define VIP_CNTRL_4_CCIR656 (1 << 4) # define VIP_CNTRL_4_656_ALT (1 << 5) # define VIP_CNTRL_4_TST_656 (1 << 6) # define VIP_CNTRL_4_TST_PAT (1 << 7) #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ # define VIP_CNTRL_5_CKCASE (1 << 0) # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) # define MAT_CONTRL_MAT_BP (1 << 2) #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ # define TBG_CNTRL_0_TOP_TGL (1 << 0) # define TBG_CNTRL_0_TOP_SEL (1 << 1) # define TBG_CNTRL_0_DE_EXT (1 << 2) # define TBG_CNTRL_0_TOP_EXT (1 << 3) # define TBG_CNTRL_0_FRAME_DIS (1 << 5) # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ # define TBG_CNTRL_1_H_TGL (1 << 0) # define TBG_CNTRL_1_V_TGL (1 << 1) # define TBG_CNTRL_1_TGL_EN (1 << 2) # define TBG_CNTRL_1_X_EXT (1 << 3) # define TBG_CNTRL_1_H_EXT (1 << 4) # define TBG_CNTRL_1_V_EXT (1 << 5) # define TBG_CNTRL_1_DWIN_DIS (1 << 6) #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ # define HVF_CNTRL_0_SM (1 << 7) # define HVF_CNTRL_0_RWB (1 << 6) # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ # define HVF_CNTRL_1_FOR (1 << 0) # define HVF_CNTRL_1_YUVBLK (1 << 1) # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ # define I2S_FORMAT(x) (((x) & 3) << 0) #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ # define AIP_CLKSEL_FS(x) (((x) & 3) << 0) # define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) # define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) /* Page 02h: PLL settings */ #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ # define PLL_SERIAL_1_SRL_FDN (1 << 0) # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ # define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ # define PLL_SERIAL_3_SRL_CCIR (1 << 0) # define PLL_SERIAL_3_SRL_DE (1 << 2) # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ # define AUDIO_DIV_SERCLK_1 0 # define AUDIO_DIV_SERCLK_2 1 # define AUDIO_DIV_SERCLK_4 2 # define AUDIO_DIV_SERCLK_8 3 # define AUDIO_DIV_SERCLK_16 4 # define AUDIO_DIV_SERCLK_32 5 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ # define SEL_CLK_SEL_CLK1 (1 << 0) # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) # define SEL_CLK_ENA_SC_CLK (1 << 3) #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ /* Page 09h: EDID Control */ #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ /* next 127 successive registers are the EDID block */ #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ /* Page 10h: information frames and packets */ #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ /* Page 11h: audio settings and content info packets */ #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ # define AIP_CNTRL_0_RST_FIFO (1 << 0) # define AIP_CNTRL_0_SWAP (1 << 1) # define AIP_CNTRL_0_LAYOUT (1 << 2) # define AIP_CNTRL_0_ACR_MAN (1 << 5) # define AIP_CNTRL_0_RST_CTS (1 << 6) #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) # define CA_I2S_HBR_CHSTAT (1 << 6) #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ # define CTS_N_K(x) (((x) & 7) << 0) # define CTS_N_M(x) (((x) & 3) << 4) #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ # define ENC_CNTRL_RST_ENC (1 << 0) # define ENC_CNTRL_RST_SEL (1 << 1) # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ # define DIP_FLAGS_ACR (1 << 0) # define DIP_FLAGS_GC (1 << 1) #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ # define DIP_IF_FLAGS_IF1 (1 << 1) # define DIP_IF_FLAGS_IF2 (1 << 2) # define DIP_IF_FLAGS_IF3 (1 << 3) # define DIP_IF_FLAGS_IF4 (1 << 4) # define DIP_IF_FLAGS_IF5 (1 << 5) #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ /* Page 12h: HDCP and OTP */ #define REG_TX3 REG(0x12, 0x9a) /* read/write */ #define REG_TX4 REG(0x12, 0x9b) /* read/write */ # define TX4_PD_RAM (1 << 1) #define REG_TX33 REG(0x12, 0xb8) /* read/write */ # define TX33_HDMI (1 << 1) /* Page 13h: Gamut related metadata packets */ /* CEC registers: (not paged) */ #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) #define REG_CEC_RXSHPDLEV 0xfe /* read */ # define CEC_RXSHPDLEV_RXSENS (1 << 0) # define CEC_RXSHPDLEV_HPD (1 << 1) #define REG_CEC_ENAMODS 0xff /* read/write */ # define CEC_ENAMODS_DIS_FRO (1 << 6) # define CEC_ENAMODS_DIS_CCLK (1 << 5) # define CEC_ENAMODS_EN_RXSENS (1 << 2) # define CEC_ENAMODS_EN_HDMI (1 << 1) # define CEC_ENAMODS_EN_CEC (1 << 0) /* Device versions: */ #define TDA9989N2 0x0101 #define TDA19989 0x0201 #define TDA19989N2 0x0202 #define TDA19988 0x0301 static void cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) { struct i2c_client *client = to_tda998x_priv(encoder)->cec; uint8_t buf[] = {addr, val}; int ret; ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); if (ret < 0) dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); } static uint8_t cec_read(struct drm_encoder *encoder, uint8_t addr) { struct i2c_client *client = to_tda998x_priv(encoder)->cec; uint8_t val; int ret; ret = i2c_master_send(client, &addr, sizeof(addr)); if (ret < 0) goto fail; ret = i2c_master_recv(client, &val, sizeof(val)); if (ret < 0) goto fail; return val; fail: dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); return 0; } static void set_page(struct drm_encoder *encoder, uint16_t reg) { struct tda998x_priv *priv = to_tda998x_priv(encoder); if (REG2PAGE(reg) != priv->current_page) { struct i2c_client *client = drm_i2c_encoder_get_client(encoder); uint8_t buf[] = { REG_CURPAGE, REG2PAGE(reg) }; int ret = i2c_master_send(client, buf, sizeof(buf)); if (ret < 0) dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); priv->current_page = REG2PAGE(reg); } } static int reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) { struct i2c_client *client = drm_i2c_encoder_get_client(encoder); uint8_t addr = REG2ADDR(reg); int ret; set_page(encoder, reg); ret = i2c_master_send(client, &addr, sizeof(addr)); if (ret < 0) goto fail; ret = i2c_master_recv(client, buf, cnt); if (ret < 0) goto fail; return ret; fail: dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); return ret; } static void reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt) { struct i2c_client *client = drm_i2c_encoder_get_client(encoder); uint8_t buf[cnt+1]; int ret; buf[0] = REG2ADDR(reg); memcpy(&buf[1], p, cnt); set_page(encoder, reg); ret = i2c_master_send(client, buf, cnt + 1); if (ret < 0) dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); } static uint8_t reg_read(struct drm_encoder *encoder, uint16_t reg) { uint8_t val = 0; reg_read_range(encoder, reg, &val, sizeof(val)); return val; } static void reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) { struct i2c_client *client = drm_i2c_encoder_get_client(encoder); uint8_t buf[] = {REG2ADDR(reg), val}; int ret; set_page(encoder, reg); ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); if (ret < 0) dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); } static void reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) { struct i2c_client *client = drm_i2c_encoder_get_client(encoder); uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; int ret; set_page(encoder, reg); ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); if (ret < 0) dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); } static void reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) { reg_write(encoder, reg, reg_read(encoder, reg) | val); } static void reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) { reg_write(encoder, reg, reg_read(encoder, reg) & ~val); } static void tda998x_reset(struct drm_encoder *encoder) { /* reset audio and i2c master: */ reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); msleep(50); reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); msleep(50); /* reset transmitter: */ reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); /* PLL registers common configuration */ reg_write(encoder, REG_PLL_SERIAL_1, 0x00); reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); reg_write(encoder, REG_PLL_SERIAL_3, 0x00); reg_write(encoder, REG_SERIALIZER, 0x00); reg_write(encoder, REG_BUFFER_OUT, 0x00); reg_write(encoder, REG_PLL_SCG1, 0x00); reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); reg_write(encoder, REG_PLL_SCGN1, 0xfa); reg_write(encoder, REG_PLL_SCGN2, 0x00); reg_write(encoder, REG_PLL_SCGR1, 0x5b); reg_write(encoder, REG_PLL_SCGR2, 0x00); reg_write(encoder, REG_PLL_SCG2, 0x10); /* Write the default value MUX register */ reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); } static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) { uint8_t sum = 0; while (bytes--) sum += *buf++; return (255 - sum) + 1; } #define HB(x) (x) #define PB(x) (HB(2) + 1 + (x)) static void tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr, uint8_t *buf, size_t size) { buf[PB(0)] = tda998x_cksum(buf, size); reg_clear(encoder, REG_DIP_IF_FLAGS, bit); reg_write_range(encoder, addr, buf, size); reg_set(encoder, REG_DIP_IF_FLAGS, bit); } static void tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p) { uint8_t buf[PB(5) + 1]; buf[HB(0)] = 0x84; buf[HB(1)] = 0x01; buf[HB(2)] = 10; buf[PB(0)] = 0; buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ buf[PB(4)] = p->audio_frame[4]; buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, sizeof(buf)); } static void tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode) { uint8_t buf[PB(13) + 1]; memset(buf, 0, sizeof(buf)); buf[HB(0)] = 0x82; buf[HB(1)] = 0x02; buf[HB(2)] = 13; buf[PB(4)] = drm_match_cea_mode(mode); tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, sizeof(buf)); } static void tda998x_audio_mute(struct drm_encoder *encoder, bool on) { if (on) { reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); } else { reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); } } static void tda998x_configure_audio(struct drm_encoder *encoder, struct drm_display_mode *mode, struct tda998x_encoder_params *p) { uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; uint32_t n; /* Enable audio ports */ reg_write(encoder, REG_ENA_AP, p->audio_cfg); reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg); /* Set audio input source */ switch (p->audio_format) { case AFMT_SPDIF: reg_write(encoder, REG_MUX_AP, 0x40); clksel_aip = AIP_CLKSEL_AIP(0); /* FS64SPDIF */ clksel_fs = AIP_CLKSEL_FS(2); cts_n = CTS_N_M(3) | CTS_N_K(3); ca_i2s = 0; break; case AFMT_I2S: reg_write(encoder, REG_MUX_AP, 0x64); clksel_aip = AIP_CLKSEL_AIP(1); /* ACLK */ clksel_fs = AIP_CLKSEL_FS(0); cts_n = CTS_N_M(3) | CTS_N_K(3); ca_i2s = CA_I2S_CA_I2S(0); break; default: BUG(); return; } reg_write(encoder, REG_AIP_CLKSEL, clksel_aip); reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); /* Enable automatic CTS generation */ reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); reg_write(encoder, REG_CTS_N, cts_n); /* * Audio input somehow depends on HDMI line rate which is * related to pixclk. Testing showed that modes with pixclk * >100MHz need a larger divider while <40MHz need the default. * There is no detailed info in the datasheet, so we just * assume 100MHz requires larger divider. */ if (mode->clock > 100000) adiv = AUDIO_DIV_SERCLK_16; else adiv = AUDIO_DIV_SERCLK_8; reg_write(encoder, REG_AUDIO_DIV, adiv); /* * This is the approximate value of N, which happens to be * the recommended values for non-coherent clocks. */ n = 128 * p->audio_sample_rate / 1000; /* Write the CTS and N values */ buf[0] = 0x44; buf[1] = 0x42; buf[2] = 0x01; buf[3] = n; buf[4] = n >> 8; buf[5] = n >> 16; reg_write_range(encoder, REG_ACR_CTS_0, buf, 6); /* Set CTS clock reference */ reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs); /* Reset CTS generator */ reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); /* Write the channel status */ buf[0] = 0x04; buf[1] = 0x00; buf[2] = 0x00; buf[3] = 0xf1; reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4); tda998x_audio_mute(encoder, true); mdelay(20); tda998x_audio_mute(encoder, false); /* Write the audio information packet */ tda998x_write_aif(encoder, p); } /* DRM encoder functions */ static void tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) { struct tda998x_priv *priv = to_tda998x_priv(encoder); struct tda998x_encoder_params *p = params; priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | VIP_CNTRL_0_SWAP_B(p->swap_b) | (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | VIP_CNTRL_1_SWAP_D(p->swap_d) | (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | VIP_CNTRL_2_SWAP_F(p->swap_f) | (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); priv->params = *p; } static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) { struct tda998x_priv *priv = to_tda998x_priv(encoder); /* we only care about on or off: */ if (mode != DRM_MODE_DPMS_ON) mode = DRM_MODE_DPMS_OFF; if (mode == priv->dpms) return; switch (mode) { case DRM_MODE_DPMS_ON: /* enable video ports, audio will be enabled later */ reg_write(encoder, REG_ENA_VP_0, 0xff); reg_write(encoder, REG_ENA_VP_1, 0xff); reg_write(encoder, REG_ENA_VP_2, 0xff); /* set muxing after enabling ports: */ reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0); reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1); reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2); break; case DRM_MODE_DPMS_OFF: /* disable video ports */ reg_write(encoder, REG_ENA_VP_0, 0x00); reg_write(encoder, REG_ENA_VP_1, 0x00); reg_write(encoder, REG_ENA_VP_2, 0x00); break; } priv->dpms = mode; } static void tda998x_encoder_save(struct drm_encoder *encoder) { DBG(""); } static void tda998x_encoder_restore(struct drm_encoder *encoder) { DBG(""); } static bool tda998x_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { return true; } static int tda998x_encoder_mode_valid(struct drm_encoder *encoder, struct drm_display_mode *mode) { return MODE_OK; } static void tda998x_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { struct tda998x_priv *priv = to_tda998x_priv(encoder); uint16_t ref_pix, ref_line, n_pix, n_line; uint16_t hs_pix_s, hs_pix_e; uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; uint16_t vwin1_line_s, vwin1_line_e; uint16_t vwin2_line_s, vwin2_line_e; uint16_t de_pix_s, de_pix_e; uint8_t reg, div, rep; /* * Internally TDA998x is using ITU-R BT.656 style sync but * we get VESA style sync. TDA998x is using a reference pixel * relative to ITU to sync to the input frame and for output * sync generation. Currently, we are using reference detection * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point * which is position of rising VS with coincident rising HS. * * Now there is some issues to take care of: * - HDMI data islands require sync-before-active * - TDA998x register values must be > 0 to be enabled * - REFLINE needs an additional offset of +1 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB * * So we add +1 to all horizontal and vertical register values, * plus an additional +3 for REFPIX as we are using RGB input only. */ n_pix = mode->htotal; n_line = mode->vtotal; hs_pix_e = mode->hsync_end - mode->hdisplay; hs_pix_s = mode->hsync_start - mode->hdisplay; de_pix_e = mode->htotal; de_pix_s = mode->htotal - mode->hdisplay; ref_pix = 3 + hs_pix_s; /* * Attached LCD controllers may generate broken sync. Allow * those to adjust the position of the rising VS edge by adding * HSKEW to ref_pix. */ if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) ref_pix += adjusted_mode->hskew; if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { ref_line = 1 + mode->vsync_start - mode->vdisplay; vwin1_line_s = mode->vtotal - mode->vdisplay - 1; vwin1_line_e = vwin1_line_s + mode->vdisplay; vs1_pix_s = vs1_pix_e = hs_pix_s; vs1_line_s = mode->vsync_start - mode->vdisplay; vs1_line_e = vs1_line_s + mode->vsync_end - mode->vsync_start; vwin2_line_s = vwin2_line_e = 0; vs2_pix_s = vs2_pix_e = 0; vs2_line_s = vs2_line_e = 0; } else { ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; vwin1_line_e = vwin1_line_s + mode->vdisplay/2; vs1_pix_s = vs1_pix_e = hs_pix_s; vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; vs1_line_e = vs1_line_s + (mode->vsync_end - mode->vsync_start)/2; vwin2_line_s = vwin1_line_s + mode->vtotal/2; vwin2_line_e = vwin2_line_s + mode->vdisplay/2; vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; vs2_line_s = vs1_line_s + mode->vtotal/2 ; vs2_line_e = vs2_line_s + (mode->vsync_end - mode->vsync_start)/2; } div = 148500 / mode->clock; /* mute the audio FIFO: */ reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); /* set HDMI HDCP mode off: */ reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); reg_clear(encoder, REG_TX33, TX33_HDMI); reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); /* no pre-filter or interpolator: */ reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | HVF_CNTRL_0_INTPOL(0)); reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | VIP_CNTRL_4_BLC(0)); reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); reg_write(encoder, REG_SERIALIZER, 0); reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ rep = 0; reg_write(encoder, REG_RPT_CNTRL, 0); reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | PLL_SERIAL_2_SRL_PR(rep)); /* set color matrix bypass flag: */ reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); /* set BIAS tmds value: */ reg_write(encoder, REG_ANA_GENERAL, 0x09); reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); /* * Sync on rising HSYNC/VSYNC */ reg_write(encoder, REG_VIP_CNTRL_3, 0); reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); /* * TDA19988 requires high-active sync at input stage, * so invert low-active sync provided by master encoder here */ if (mode->flags & DRM_MODE_FLAG_NHSYNC) reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); if (mode->flags & DRM_MODE_FLAG_NVSYNC) reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); /* * Always generate sync polarity relative to input sync and * revert input stage toggled sync at output stage */ reg = TBG_CNTRL_1_TGL_EN; if (mode->flags & DRM_MODE_FLAG_NHSYNC) reg |= TBG_CNTRL_1_H_TGL; if (mode->flags & DRM_MODE_FLAG_NVSYNC) reg |= TBG_CNTRL_1_V_TGL; reg_write(encoder, REG_TBG_CNTRL_1, reg); reg_write(encoder, REG_VIDFORMAT, 0x00); reg_write16(encoder, REG_REFPIX_MSB, ref_pix); reg_write16(encoder, REG_REFLINE_MSB, ref_line); reg_write16(encoder, REG_NPIX_MSB, n_pix); reg_write16(encoder, REG_NLINE_MSB, n_line); reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s); reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e); reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e); reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s); reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e); reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e); reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s); reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e); reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s); reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e); reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s); reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e); reg_write16(encoder, REG_DE_START_MSB, de_pix_s); reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e); if (priv->rev == TDA19988) { /* let incoming pixels fill the active space (if any) */ reg_write(encoder, REG_ENABLE_SPACE, 0x01); } /* must be last register set: */ reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); /* Only setup the info frames if the sink is HDMI */ if (priv->is_hdmi_sink) { /* We need to turn HDMI HDCP stuff on to get audio through */ reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); reg_set(encoder, REG_TX33, TX33_HDMI); tda998x_write_avi(encoder, adjusted_mode); if (priv->params.audio_cfg) tda998x_configure_audio(encoder, adjusted_mode, &priv->params); } } static enum drm_connector_status tda998x_encoder_detect(struct drm_encoder *encoder, struct drm_connector *connector) { uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : connector_status_disconnected; } static int read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) { uint8_t offset, segptr; int ret, i; /* enable EDID read irq: */ reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); offset = (blk & 1) ? 128 : 0; segptr = blk / 2; reg_write(encoder, REG_DDC_ADDR, 0xa0); reg_write(encoder, REG_DDC_OFFS, offset); reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); reg_write(encoder, REG_DDC_SEGM, segptr); /* enable reading EDID: */ reg_write(encoder, REG_EDID_CTRL, 0x1); /* flag must be cleared by sw: */ reg_write(encoder, REG_EDID_CTRL, 0x0); /* wait for block read to complete: */ for (i = 100; i > 0; i--) { uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); if (val & INT_FLAGS_2_EDID_BLK_RD) break; msleep(1); } if (i == 0) return -ETIMEDOUT; ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); if (ret != EDID_LENGTH) { dev_err(encoder->dev->dev, "failed to read edid block %d: %d", blk, ret); return ret; } reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); return 0; } static uint8_t * do_get_edid(struct drm_encoder *encoder) { struct tda998x_priv *priv = to_tda998x_priv(encoder); int j = 0, valid_extensions = 0; uint8_t *block, *new; bool print_bad_edid = drm_debug & DRM_UT_KMS; if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) return NULL; if (priv->rev == TDA19988) reg_clear(encoder, REG_TX4, TX4_PD_RAM); /* base block fetch */ if (read_edid_block(encoder, block, 0)) goto fail; if (!drm_edid_block_valid(block, 0, print_bad_edid)) goto fail; /* if there's no extensions, we're done */ if (block[0x7e] == 0) goto done; new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); if (!new) goto fail; block = new; for (j = 1; j <= block[0x7e]; j++) { uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; if (read_edid_block(encoder, ext_block, j)) goto fail; if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) goto fail; valid_extensions++; } if (valid_extensions != block[0x7e]) { block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; block[0x7e] = valid_extensions; new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); if (!new) goto fail; block = new; } done: if (priv->rev == TDA19988) reg_set(encoder, REG_TX4, TX4_PD_RAM); return block; fail: if (priv->rev == TDA19988) reg_set(encoder, REG_TX4, TX4_PD_RAM); dev_warn(encoder->dev->dev, "failed to read EDID\n"); kfree(block); return NULL; } static int tda998x_encoder_get_modes(struct drm_encoder *encoder, struct drm_connector *connector) { struct tda998x_priv *priv = to_tda998x_priv(encoder); struct edid *edid = (struct edid *)do_get_edid(encoder); int n = 0; if (edid) { drm_mode_connector_update_edid_property(connector, edid); n = drm_add_edid_modes(connector, edid); priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); kfree(edid); } return n; } static int tda998x_encoder_create_resources(struct drm_encoder *encoder, struct drm_connector *connector) { DBG(""); return 0; } static int tda998x_encoder_set_property(struct drm_encoder *encoder, struct drm_connector *connector, struct drm_property *property, uint64_t val) { DBG(""); return 0; } static void tda998x_encoder_destroy(struct drm_encoder *encoder) { struct tda998x_priv *priv = to_tda998x_priv(encoder); drm_i2c_encoder_destroy(encoder); kfree(priv); } static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { .set_config = tda998x_encoder_set_config, .destroy = tda998x_encoder_destroy, .dpms = tda998x_encoder_dpms, .save = tda998x_encoder_save, .restore = tda998x_encoder_restore, .mode_fixup = tda998x_encoder_mode_fixup, .mode_valid = tda998x_encoder_mode_valid, .mode_set = tda998x_encoder_mode_set, .detect = tda998x_encoder_detect, .get_modes = tda998x_encoder_get_modes, .create_resources = tda998x_encoder_create_resources, .set_property = tda998x_encoder_set_property, }; /* I2C driver functions */ static int tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) { return 0; } static int tda998x_remove(struct i2c_client *client) { return 0; } static int tda998x_encoder_init(struct i2c_client *client, struct drm_device *dev, struct drm_encoder_slave *encoder_slave) { struct drm_encoder *encoder = &encoder_slave->base; struct tda998x_priv *priv; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); priv->current_page = 0; priv->cec = i2c_new_dummy(client->adapter, 0x34); priv->dpms = DRM_MODE_DPMS_OFF; encoder_slave->slave_priv = priv; encoder_slave->slave_funcs = &tda998x_encoder_funcs; /* wake up the device: */ cec_write(encoder, REG_CEC_ENAMODS, CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); tda998x_reset(encoder); /* read version: */ priv->rev = reg_read(encoder, REG_VERSION_LSB) | reg_read(encoder, REG_VERSION_MSB) << 8; /* mask off feature bits: */ priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ switch (priv->rev) { case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; case TDA19989: dev_info(dev->dev, "found TDA19989"); break; case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; case TDA19988: dev_info(dev->dev, "found TDA19988"); break; default: DBG("found unsupported device: %04x", priv->rev); goto fail; } /* after reset, enable DDC: */ reg_write(encoder, REG_DDC_DISABLE, 0x00); /* set clock on DDC channel: */ reg_write(encoder, REG_TX3, 39); /* if necessary, disable multi-master: */ if (priv->rev == TDA19989) reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); return 0; fail: /* if encoder_init fails, the encoder slave is never registered, * so cleanup here: */ if (priv->cec) i2c_unregister_device(priv->cec); kfree(priv); encoder_slave->slave_priv = NULL; encoder_slave->slave_funcs = NULL; return -ENXIO; } static struct i2c_device_id tda998x_ids[] = { { "tda998x", 0 }, { } }; MODULE_DEVICE_TABLE(i2c, tda998x_ids); static struct drm_i2c_encoder_driver tda998x_driver = { .i2c_driver = { .probe = tda998x_probe, .remove = tda998x_remove, .driver = { .name = "tda998x", }, .id_table = tda998x_ids, }, .encoder_init = tda998x_encoder_init, }; /* Module initialization */ static int __init tda998x_init(void) { DBG(""); return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); } static void __exit tda998x_exit(void) { DBG(""); drm_i2c_encoder_unregister(&tda998x_driver); } MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); MODULE_LICENSE("GPL"); module_init(tda998x_init); module_exit(tda998x_exit); |