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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 | /* * Copyright 2013 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #include "skeleton.dtsi" #include "vf610-pinfunc.h" #include <dt-bindings/clock/vf610-clock.h> / { aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a5"; device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; }; }; clocks { #address-cells = <1>; #size-cells = <0>; sxosc { compatible = "fixed-clock"; clock-frequency = <32768>; }; fxosc { compatible = "fixed-clock"; clock-frequency = <24000000>; }; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&intc>; ranges; aips0: aips-bus@40000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; reg = <0x40000000 0x70000>; ranges; intc: interrupt-controller@40002000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; reg = <0x40003000 0x1000>, <0x40002100 0x100>; }; L2: l2-cache@40006000 { compatible = "arm,pl310-cache"; reg = <0x40006000 0x1000>; cache-unified; cache-level = <2>; arm,data-latency = <1 1 1>; arm,tag-latency = <2 2 2>; }; uart0: serial@40027000 { compatible = "fsl,vf610-lpuart"; reg = <0x40027000 0x1000>; interrupts = <0 61 0x00>; clocks = <&clks VF610_CLK_UART0>; clock-names = "ipg"; status = "disabled"; }; uart1: serial@40028000 { compatible = "fsl,vf610-lpuart"; reg = <0x40028000 0x1000>; interrupts = <0 62 0x04>; clocks = <&clks VF610_CLK_UART1>; clock-names = "ipg"; status = "disabled"; }; uart2: serial@40029000 { compatible = "fsl,vf610-lpuart"; reg = <0x40029000 0x1000>; interrupts = <0 63 0x04>; clocks = <&clks VF610_CLK_UART2>; clock-names = "ipg"; status = "disabled"; }; uart3: serial@4002a000 { compatible = "fsl,vf610-lpuart"; reg = <0x4002a000 0x1000>; interrupts = <0 64 0x04>; clocks = <&clks VF610_CLK_UART3>; clock-names = "ipg"; status = "disabled"; }; sai2: sai@40031000 { compatible = "fsl,vf610-sai"; reg = <0x40031000 0x1000>; interrupts = <0 86 0x04>; clocks = <&clks VF610_CLK_SAI2>; clock-names = "sai"; status = "disabled"; }; pit: pit@40037000 { compatible = "fsl,vf610-pit"; reg = <0x40037000 0x1000>; interrupts = <0 39 0x04>; clocks = <&clks VF610_CLK_PIT>; clock-names = "pit"; }; wdog@4003e000 { compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; reg = <0x4003e000 0x1000>; clocks = <&clks VF610_CLK_WDT>; clock-names = "wdog"; }; qspi0: quadspi@40044000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-qspi"; reg = <0x40044000 0x1000>; interrupts = <0 24 0x04>; clocks = <&clks VF610_CLK_QSPI0_EN>, <&clks VF610_CLK_QSPI0>; clock-names = "qspi_en", "qspi"; status = "disabled"; }; iomuxc: iomuxc@40048000 { compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; #gpio-range-cells = <3>; /* functions and groups pins */ dcu0 { pinctrl_dcu0_1: dcu0grp_1 { fsl,pins = < VF610_PAD_PTB8__GPIO_30 0x42 VF610_PAD_PTE0__DCU0_HSYNC 0x42 VF610_PAD_PTE1__DCU0_VSYNC 0x42 VF610_PAD_PTE2__DCU0_PCLK 0x42 VF610_PAD_PTE4__DCU0_DE 0x42 VF610_PAD_PTE5__DCU0_R0 0x42 VF610_PAD_PTE6__DCU0_R1 0x42 VF610_PAD_PTE7__DCU0_R2 0x42 VF610_PAD_PTE8__DCU0_R3 0x42 VF610_PAD_PTE9__DCU0_R4 0x42 VF610_PAD_PTE10__DCU0_R5 0x42 VF610_PAD_PTE11__DCU0_R6 0x42 VF610_PAD_PTE12__DCU0_R7 0x42 VF610_PAD_PTE13__DCU0_G0 0x42 VF610_PAD_PTE14__DCU0_G1 0x42 VF610_PAD_PTE15__DCU0_G2 0x42 VF610_PAD_PTE16__DCU0_G3 0x42 VF610_PAD_PTE17__DCU0_G4 0x42 VF610_PAD_PTE18__DCU0_G5 0x42 VF610_PAD_PTE19__DCU0_G6 0x42 VF610_PAD_PTE20__DCU0_G7 0x42 VF610_PAD_PTE21__DCU0_B0 0x42 VF610_PAD_PTE22__DCU0_B1 0x42 VF610_PAD_PTE23__DCU0_B2 0x42 VF610_PAD_PTE24__DCU0_B3 0x42 VF610_PAD_PTE25__DCU0_B4 0x42 VF610_PAD_PTE26__DCU0_B5 0x42 VF610_PAD_PTE27__DCU0_B6 0x42 VF610_PAD_PTE28__DCU0_B7 0x42 >; }; }; dspi0 { pinctrl_dspi0_1: dspi0grp_1 { fsl,pins = < VF610_PAD_PTB19__DSPI0_CS0 0x1182 VF610_PAD_PTB20__DSPI0_SIN 0x1181 VF610_PAD_PTB21__DSPI0_SOUT 0x1182 VF610_PAD_PTB22__DSPI0_SCK 0x1182 >; }; }; esdhc1 { pinctrl_esdhc1_1: esdhc1grp_1 { fsl,pins = < VF610_PAD_PTA24__ESDHC1_CLK 0x31ef VF610_PAD_PTA25__ESDHC1_CMD 0x31ef VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef VF610_PAD_PTA7__GPIO_134 0x219d >; }; }; fec0 { pinctrl_fec0_1: fec0grp_1 { fsl,pins = < VF610_PAD_PTA6__RMII_CLKIN 0x30d1 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 >; }; }; fec1 { pinctrl_fec1_1: fec1grp_1 { fsl,pins = < VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 >; }; }; i2c0 { pinctrl_i2c0_1: i2c0grp_1 { fsl,pins = < VF610_PAD_PTB14__I2C0_SCL 0x30d3 VF610_PAD_PTB15__I2C0_SDA 0x30d3 >; }; }; pwm0 { pinctrl_pwm0_1: pwm0grp_1 { fsl,pins = < VF610_PAD_PTB0__FTM0_CH0 0x1582 VF610_PAD_PTB1__FTM0_CH1 0x1582 VF610_PAD_PTB2__FTM0_CH2 0x1582 VF610_PAD_PTB3__FTM0_CH3 0x1582 VF610_PAD_PTB6__FTM0_CH6 0x1582 VF610_PAD_PTB7__FTM0_CH7 0x1582 >; }; }; qspi0 { pinctrl_qspi0_1: qspi0grp_1 { fsl,pins = < VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b VF610_PAD_PTD1__QSPI0_A_CS0 0x307f VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073 VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073 VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073 VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b VF610_PAD_PTD8__QSPI0_B_CS0 0x307f VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073 VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073 VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073 VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b >; }; }; sai2 { pinctrl_sai2_1: sai2grp_1 { fsl,pins = < VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed >; }; }; uart1 { pinctrl_uart1_1: uart1grp_1 { fsl,pins = < VF610_PAD_PTB4__UART1_TX 0x21a2 VF610_PAD_PTB5__UART1_RX 0x21a1 >; }; }; usbvbus { pinctrl_usbvbus_1: usbvbusgrp_1 { fsl,pins = < VF610_PAD_PTA24__USB1_VBUS_EN 0x219c VF610_PAD_PTA16__USB0_VBUS_EN 0x219c >; }; }; }; gpio1: gpio@40049000 { compatible = "fsl,vf610-gpio"; reg = <0x40049000 0x1000 0x400ff000 0x40>; interrupts = <0 107 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 0 32>; }; gpio2: gpio@4004a000 { compatible = "fsl,vf610-gpio"; reg = <0x4004a000 0x1000 0x400ff040 0x40>; interrupts = <0 108 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 32 32>; }; gpio3: gpio@4004b000 { compatible = "fsl,vf610-gpio"; reg = <0x4004b000 0x1000 0x400ff080 0x40>; interrupts = <0 109 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 64 32>; }; gpio4: gpio@4004c000 { compatible = "fsl,vf610-gpio"; reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; interrupts = <0 110 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 96 32>; }; gpio5: gpio@4004d000 { compatible = "fsl,vf610-gpio"; reg = <0x4004d000 0x1000 0x400ff100 0x40>; interrupts = <0 111 0x04>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 128 7>; }; anatop@40050000 { compatible = "fsl,vf610-anatop"; reg = <0x40050000 0x1000>; }; i2c0: i2c@40066000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-i2c"; reg = <0x40066000 0x1000>; interrupts =<0 71 0x04>; clocks = <&clks VF610_CLK_I2C0>; clock-names = "ipg"; status = "disabled"; }; clks: ccm@4006b000 { compatible = "fsl,vf610-ccm"; reg = <0x4006b000 0x1000>; #clock-cells = <1>; }; }; aips1: aips-bus@40080000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x40080000 0x80000>; ranges; uart4: serial@400a9000 { compatible = "fsl,vf610-lpuart"; reg = <0x400a9000 0x1000>; interrupts = <0 65 0x04>; clocks = <&clks VF610_CLK_UART4>; clock-names = "ipg"; status = "disabled"; }; uart5: serial@400aa000 { compatible = "fsl,vf610-lpuart"; reg = <0x400aa000 0x1000>; interrupts = <0 66 0x04>; clocks = <&clks VF610_CLK_UART5>; clock-names = "ipg"; status = "disabled"; }; fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; interrupts = <0 78 0x04>; clocks = <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET0>, <&clks VF610_CLK_ENET>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; fec1: ethernet@400d1000 { compatible = "fsl,mvf600-fec"; reg = <0x400d1000 0x1000>; interrupts = <0 79 0x04>; clocks = <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET1>, <&clks VF610_CLK_ENET>; clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; }; }; }; |