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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 | #ifndef __ASM_ARM_CPUTYPE_H #define __ASM_ARM_CPUTYPE_H #include <linux/stringify.h> #include <linux/kernel.h> #define CPUID_ID 0 #define CPUID_CACHETYPE 1 #define CPUID_TCM 2 #define CPUID_TLBTYPE 3 #define CPUID_MPIDR 5 #define CPUID_EXT_PFR0 "c1, 0" #define CPUID_EXT_PFR1 "c1, 1" #define CPUID_EXT_DFR0 "c1, 2" #define CPUID_EXT_AFR0 "c1, 3" #define CPUID_EXT_MMFR0 "c1, 4" #define CPUID_EXT_MMFR1 "c1, 5" #define CPUID_EXT_MMFR2 "c1, 6" #define CPUID_EXT_MMFR3 "c1, 7" #define CPUID_EXT_ISAR0 "c2, 0" #define CPUID_EXT_ISAR1 "c2, 1" #define CPUID_EXT_ISAR2 "c2, 2" #define CPUID_EXT_ISAR3 "c2, 3" #define CPUID_EXT_ISAR4 "c2, 4" #define CPUID_EXT_ISAR5 "c2, 5" #define MPIDR_SMP_BITMASK (0x3 << 30) #define MPIDR_SMP_VALUE (0x2 << 30) #define MPIDR_MT_BITMASK (0x1 << 24) #define MPIDR_HWID_BITMASK 0xFFFFFF #define MPIDR_INVALID (~MPIDR_HWID_BITMASK) #define MPIDR_LEVEL_BITS 8 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_IMP_INTEL 0x69 #define ARM_CPU_PART_ARM1136 0xB360 #define ARM_CPU_PART_ARM1156 0xB560 #define ARM_CPU_PART_ARM1176 0xB760 #define ARM_CPU_PART_ARM11MPCORE 0xB020 #define ARM_CPU_PART_CORTEX_A8 0xC080 #define ARM_CPU_PART_CORTEX_A9 0xC090 #define ARM_CPU_PART_CORTEX_A5 0xC050 #define ARM_CPU_PART_CORTEX_A15 0xC0F0 #define ARM_CPU_PART_CORTEX_A7 0xC070 #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 #define ARM_CPU_XSCALE_ARCH_V2 0x4000 #define ARM_CPU_XSCALE_ARCH_V3 0x6000 /* Qualcomm implemented cores */ #define ARM_CPU_PART_SCORPION 0x510002d0 extern unsigned int processor_id; #ifdef CONFIG_CPU_CP15 #define read_cpuid(reg) \ ({ \ unsigned int __val; \ asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ : "=r" (__val) \ : \ : "cc"); \ __val; \ }) #define read_cpuid_ext(ext_reg) \ ({ \ unsigned int __val; \ asm("mrc p15, 0, %0, c0, " ext_reg \ : "=r" (__val) \ : \ : "cc"); \ __val; \ }) #else /* ifdef CONFIG_CPU_CP15 */ /* * read_cpuid and read_cpuid_ext should only ever be called on machines that * have cp15 so warn on other usages. */ #define read_cpuid(reg) \ ({ \ WARN_ON_ONCE(1); \ 0; \ }) #define read_cpuid_ext(reg) read_cpuid(reg) #endif /* ifdef CONFIG_CPU_CP15 / else */ #ifdef CONFIG_CPU_CP15 /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID * rather than directly reading processor_id or read_cpuid() directly. */ static inline unsigned int __attribute_const__ read_cpuid_id(void) { return read_cpuid(CPUID_ID); } #else /* ifdef CONFIG_CPU_CP15 */ static inline unsigned int __attribute_const__ read_cpuid_id(void) { return processor_id; } #endif /* ifdef CONFIG_CPU_CP15 / else */ static inline unsigned int __attribute_const__ read_cpuid_implementor(void) { return (read_cpuid_id() & 0xFF000000) >> 24; } static inline unsigned int __attribute_const__ read_cpuid_part_number(void) { return read_cpuid_id() & 0xFFF0; } static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) { return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK; } static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); } static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) { return read_cpuid(CPUID_TCM); } static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) { return read_cpuid(CPUID_MPIDR); } /* * Intel's XScale3 core supports some v6 features (supersections, L2) * but advertises itself as v5 as it does not support the v6 ISA. For * this reason, we need a way to explicitly test for this type of CPU. */ #ifndef CONFIG_CPU_XSC3 #define cpu_is_xsc3() 0 #else static inline int cpu_is_xsc3(void) { unsigned int id; id = read_cpuid_id() & 0xffffe000; /* It covers both Intel ID and Marvell ID */ if ((id == 0x69056000) || (id == 0x56056000)) return 1; return 0; } #endif #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) #define cpu_is_xscale() 0 #else #define cpu_is_xscale() 1 #endif #endif |