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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 | /* * Manroland mucmc52 board Device Tree Source * * Copyright (C) 2009 DENX Software Engineering GmbH * Heiko Schocher <hs@denx.de> * Copyright 2006-2007 Secret Lab Technologies Ltd. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ /dts-v1/; / { model = "manroland,mucmc52"; compatible = "manroland,mucmc52"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&mpc5200_pic>; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,5200@0 { device_type = "cpu"; reg = <0>; d-cache-line-size = <32>; i-cache-line-size = <32>; d-cache-size = <0x4000>; // L1, 16K i-cache-size = <0x4000>; // L1, 16K timebase-frequency = <0>; // from bootloader bus-frequency = <0>; // from bootloader clock-frequency = <0>; // from bootloader }; }; memory { device_type = "memory"; reg = <0x00000000 0x04000000>; // 64MB }; soc5200@f0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc5200b-immr"; ranges = <0 0xf0000000 0x0000c000>; reg = <0xf0000000 0x00000100>; bus-frequency = <0>; // from bootloader system-frequency = <0>; // from bootloader cdm@200 { compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; reg = <0x200 0x38>; }; mpc5200_pic: interrupt-controller@500 { // 5200 interrupts are encoded into two levels; interrupt-controller; #interrupt-cells = <3>; compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; reg = <0x500 0x80>; }; gpt0: timer@600 { // GPT 0 in GPIO mode compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; reg = <0x600 0x10>; interrupts = <1 9 0>; gpio-controller; #gpio-cells = <2>; }; gpt1: timer@610 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; reg = <0x610 0x10>; interrupts = <1 10 0>; gpio-controller; #gpio-cells = <2>; }; gpt2: timer@620 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; reg = <0x620 0x10>; interrupts = <1 11 0>; gpio-controller; #gpio-cells = <2>; }; gpt3: timer@630 { // General Purpose Timer in GPIO mode compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; reg = <0x630 0x10>; interrupts = <1 12 0>; gpio-controller; #gpio-cells = <2>; }; gpio_simple: gpio@b00 { compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; reg = <0xb00 0x40>; interrupts = <1 7 0>; gpio-controller; #gpio-cells = <2>; }; gpio_wkup: gpio@c00 { compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; reg = <0xc00 0x40>; interrupts = <1 8 0 0 3 0>; gpio-controller; #gpio-cells = <2>; }; dma-controller@1200 { compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; reg = <0x1200 0x80>; interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 3 4 0 3 5 0 3 6 0 3 7 0 3 8 0 3 9 0 3 10 0 3 11 0 3 12 0 3 13 0 3 14 0 3 15 0>; }; xlb@1f00 { compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; reg = <0x1f00 0x100>; }; serial@2000 { /* PSC1 in UART mode */ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; reg = <0x2000 0x100>; interrupts = <2 1 0>; }; serial@2200 { /* PSC2 in UART mode */ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; reg = <0x2200 0x100>; interrupts = <2 2 0>; }; serial@2c00 { /* PSC6 in UART mode */ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; reg = <0x2c00 0x100>; interrupts = <2 4 0>; }; ethernet@3000 { compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; reg = <0x3000 0x400>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <2 5 0>; phy-handle = <&phy0>; }; mdio@3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. phy0: ethernet-phy@0 { compatible = "intel,lxt971"; reg = <0>; }; }; ata@3a00 { compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; reg = <0x3a00 0x100>; interrupts = <2 7 0>; }; i2c@3d40 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; reg = <0x3d40 0x40>; interrupts = <2 16 0>; hwmon@2c { compatible = "ad,adm9240"; reg = <0x2c>; }; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; sram@8000 { compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; reg = <0x8000 0x4000>; }; }; pci@f0000d00 { #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; reg = <0xf0000d00 0x100>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x10 */ 0x8000 0 0 1 &mpc5200_pic 0 3 3 0x8000 0 0 2 &mpc5200_pic 0 3 3 0x8000 0 0 3 &mpc5200_pic 0 2 3 0x8000 0 0 4 &mpc5200_pic 0 1 3 >; clock-frequency = <0>; // From boot loader interrupts = <2 8 0 2 9 0 2 10 0>; bus-range = <0 0>; ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000 0x02000000 0 0x90000000 0x90000000 0 0x10000000 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; }; localbus { compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0xff800000 0x00800000 1 0 0x80000000 0x00800000 3 0 0x80000000 0x00800000>; flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x00800000>; bank-width = <4>; device-width = <2>; #size-cells = <1>; #address-cells = <1>; partition@0 { label = "DTS"; reg = <0x0 0x00100000>; }; partition@100000 { label = "Kernel"; reg = <0x100000 0x00200000>; }; partition@300000 { label = "RootFS"; reg = <0x00300000 0x00200000>; }; partition@500000 { label = "user"; reg = <0x00500000 0x00200000>; }; partition@700000 { label = "U-Boot"; reg = <0x00700000 0x00040000>; }; partition@740000 { label = "Env"; reg = <0x00740000 0x00020000>; }; partition@760000 { label = "red. Env"; reg = <0x00760000 0x00020000>; }; partition@780000 { label = "reserve"; reg = <0x00780000 0x00080000>; }; }; simple100: gpio-controller-100@3,600100 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600100 0x1>; gpio-controller; #gpio-cells = <2>; }; simple104: gpio-controller-104@3,600104 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600104 0x1>; gpio-controller; #gpio-cells = <2>; }; simple200: gpio-controller-200@3,600200 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600200 0x1>; gpio-controller; #gpio-cells = <2>; }; simple201: gpio-controller-201@3,600201 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600201 0x1>; gpio-controller; #gpio-cells = <2>; }; simple202: gpio-controller-202@3,600202 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600202 0x1>; gpio-controller; #gpio-cells = <2>; }; simple203: gpio-controller-203@3,600203 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600203 0x1>; gpio-controller; #gpio-cells = <2>; }; simple204: gpio-controller-204@3,600204 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600204 0x1>; gpio-controller; #gpio-cells = <2>; }; simple206: gpio-controller-206@3,600206 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600206 0x1>; gpio-controller; #gpio-cells = <2>; }; simple207: gpio-controller-207@3,600207 { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x00600207 0x1>; gpio-controller; #gpio-cells = <2>; }; simple20f: gpio-controller-20f@3,60020f { compatible = "manroland,mucmc52-aux-gpio"; reg = <3 0x0060020f 0x1>; gpio-controller; #gpio-cells = <2>; }; }; }; |