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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 | /* * MPC8569E MDS Device Tree Source * * Copyright (C) 2009 Freescale Semiconductor Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ /dts-v1/; / { model = "MPC8569EMDS"; compatible = "fsl,MPC8569EMDS"; #address-cells = <1>; #size-cells = <1>; aliases { serial0 = &serial0; serial1 = &serial1; ethernet0 = &enet0; ethernet1 = &enet1; ethernet2 = &enet2; ethernet3 = &enet3; ethernet5 = &enet5; ethernet7 = &enet7; pci1 = &pci1; rapidio0 = &rio0; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8569@0 { device_type = "cpu"; reg = <0x0>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <0x8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; next-level-cache = <&L2>; }; }; memory { device_type = "memory"; }; localbus@e0005000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; reg = <0xe0005000 0x1000>; interrupts = <19 2>; interrupt-parent = <&mpic>; ranges = <0x0 0x0 0xfe000000 0x02000000 0x1 0x0 0xf8000000 0x00008000 0x2 0x0 0xf0000000 0x04000000 0x3 0x0 0xfc000000 0x00008000 0x4 0x0 0xf8008000 0x00008000 0x5 0x0 0xf8010000 0x00008000>; nor@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; reg = <0x0 0x0 0x02000000>; bank-width = <1>; device-width = <1>; partition@0 { label = "ramdisk"; reg = <0x00000000 0x01c00000>; }; partition@1c00000 { label = "kernel"; reg = <0x01c00000 0x002e0000>; }; partiton@1ee0000 { label = "dtb"; reg = <0x01ee0000 0x00020000>; }; partition@1f00000 { label = "firmware"; reg = <0x01f00000 0x00080000>; read-only; }; partition@1f80000 { label = "u-boot"; reg = <0x01f80000 0x00080000>; read-only; }; }; bcsr@1,0 { compatible = "fsl,mpc8569mds-bcsr"; reg = <1 0 0x8000>; }; nand@3,0 { compatible = "fsl,mpc8569-fcm-nand", "fsl,elbc-fcm-nand"; reg = <3 0 0x8000>; }; pib@4,0 { compatible = "fsl,mpc8569mds-pib"; reg = <4 0 0x8000>; }; pib@5,0 { compatible = "fsl,mpc8569mds-pib"; reg = <5 0 0x8000>; }; }; soc@e0000000 { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8569-immr", "simple-bus"; ranges = <0x0 0xe0000000 0x100000>; bus-frequency = <0>; ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; ecm@1000 { compatible = "fsl,mpc8569-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <17 2>; interrupt-parent = <&mpic>; }; memory-controller@2000 { compatible = "fsl,mpc8569-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; i2c@3000 { #address-cells = <1>; #size-cells = <0>; cell-index = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; rtc@68 { compatible = "dallas,ds1374"; reg = <0x68>; }; }; i2c@3100 { #address-cells = <1>; #size-cells = <0>; cell-index = <1>; compatible = "fsl-i2c"; reg = <0x3100 0x100>; interrupts = <43 2>; interrupt-parent = <&mpic>; dfsrr; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "ns16550"; reg = <0x4500 0x100>; clock-frequency = <0>; interrupts = <42 2>; interrupt-parent = <&mpic>; }; serial1: serial@4600 { cell-index = <1>; device_type = "serial"; compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; interrupts = <42 2>; interrupt-parent = <&mpic>; }; L2: l2-cache-controller@20000 { compatible = "fsl,mpc8569-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x80000>; // L2, 512K interrupt-parent = <&mpic>; interrupts = <16 2>; }; dma@21300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma"; reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8569-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8569-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8569-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8569-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <23 2>; }; }; sdhci@2e000 { compatible = "fsl,mpc8569-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <72 0x8>; interrupt-parent = <&mpic>; /* Filled in by U-Boot */ clock-frequency = <0>; status = "disabled"; sdhci,1-bit-only; }; crypto@30000 { compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; reg = <0x30000 0x10000>; interrupts = <45 2 58 2>; interrupt-parent = <&mpic>; fsl,num-channels = <4>; fsl,channel-fifo-len = <24>; fsl,exec-units-mask = <0xbfe>; fsl,descriptor-types-mask = <0x3ab0ebf>; }; mpic: pic@40000 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; }; msi@41600 { compatible = "fsl,mpc8568-msi", "fsl,mpic-msi"; reg = <0x41600 0x80>; msi-available-ranges = <0 0x100>; interrupts = < 0xe0 0 0xe1 0 0xe2 0 0xe3 0 0xe4 0 0xe5 0 0xe6 0 0xe7 0>; interrupt-parent = <&mpic>; }; global-utilities@e0000 { compatible = "fsl,mpc8569-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; par_io@e0100 { #address-cells = <1>; #size-cells = <1>; reg = <0xe0100 0x100>; ranges = <0x0 0xe0100 0x100>; device_type = "par_io"; num-ports = <7>; qe_pio_e: gpio-controller@80 { #gpio-cells = <2>; compatible = "fsl,mpc8569-qe-pario-bank", "fsl,mpc8323-qe-pario-bank"; reg = <0x80 0x18>; gpio-controller; }; pio1: ucc_pin@01 { pio-map = < /* port pin dir open_drain assignment has_irq */ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */ 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */ 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */ 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */ 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */ 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */ 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */ 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */ }; pio2: ucc_pin@02 { pio-map = < /* port pin dir open_drain assignment has_irq */ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */ 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */ 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */ 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */ 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */ 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */ 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */ 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */ 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */ 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */ 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */ 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */ }; pio3: ucc_pin@03 { pio-map = < /* port pin dir open_drain assignment has_irq */ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */ 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */ 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */ 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */ 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */ 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */ 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */ 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */ 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */ 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */ 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */ 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */ }; pio4: ucc_pin@04 { pio-map = < /* port pin dir open_drain assignment has_irq */ 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */ 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */ 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */ 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */ 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */ 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */ 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */ 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */ 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */ 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */ 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */ 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */ }; }; }; qe@e0080000 { #address-cells = <1>; #size-cells = <1>; device_type = "qe"; compatible = "fsl,qe"; ranges = <0x0 0xe0080000 0x40000>; reg = <0xe0080000 0x480>; brg-frequency = <0>; bus-frequency = <0>; fsl,qe-num-riscs = <4>; fsl,qe-num-snums = <46>; qeic: interrupt-controller@80 { interrupt-controller; compatible = "fsl,qe-ic"; #address-cells = <0>; #interrupt-cells = <1>; reg = <0x80 0x80>; interrupts = <46 2 46 2>; //high:30 low:30 interrupt-parent = <&mpic>; }; spi@4c0 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mpc8569-qe-spi", "fsl,spi"; reg = <0x4c0 0x40>; cell-index = <0>; interrupts = <2>; interrupt-parent = <&qeic>; gpios = <&qe_pio_e 30 0>; mode = "cpu-qe"; serial-flash@0 { compatible = "stm,m25p40"; reg = <0>; spi-max-frequency = <25000000>; }; }; spi@500 { cell-index = <1>; compatible = "fsl,spi"; reg = <0x500 0x40>; interrupts = <1>; interrupt-parent = <&qeic>; mode = "cpu"; }; enet0: ucc@2000 { device_type = "network"; compatible = "ucc_geth"; cell-index = <1>; reg = <0x2000 0x200>; interrupts = <32>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk12"; pio-handle = <&pio1>; phy-handle = <&qe_phy0>; phy-connection-type = "rgmii-id"; }; mdio@2120 { #address-cells = <1>; #size-cells = <0>; reg = <0x2120 0x18>; compatible = "fsl,ucc-mdio"; qe_phy0: ethernet-phy@07 { interrupt-parent = <&mpic>; interrupts = <1 1>; reg = <0x7>; device_type = "ethernet-phy"; }; qe_phy1: ethernet-phy@01 { interrupt-parent = <&mpic>; interrupts = <2 1>; reg = <0x1>; device_type = "ethernet-phy"; }; qe_phy2: ethernet-phy@02 { interrupt-parent = <&mpic>; interrupts = <3 1>; reg = <0x2>; device_type = "ethernet-phy"; }; qe_phy3: ethernet-phy@03 { interrupt-parent = <&mpic>; interrupts = <4 1>; reg = <0x3>; device_type = "ethernet-phy"; }; qe_phy5: ethernet-phy@04 { interrupt-parent = <&mpic>; reg = <0x04>; device_type = "ethernet-phy"; }; qe_phy7: ethernet-phy@06 { interrupt-parent = <&mpic>; reg = <0x6>; device_type = "ethernet-phy"; }; tbi-phy@11 { reg = <0x11>; device_type = "tbi-phy"; }; }; mdio@3520 { #address-cells = <1>; #size-cells = <0>; reg = <0x3520 0x18>; compatible = "fsl,ucc-mdio"; tbi0: tbi-phy@15 { reg = <0x15>; device_type = "tbi-phy"; }; }; mdio@3720 { #address-cells = <1>; #size-cells = <0>; reg = <0x3720 0x38>; compatible = "fsl,ucc-mdio"; tbi1: tbi-phy@17 { reg = <0x17>; device_type = "tbi-phy"; }; }; enet2: ucc@2200 { device_type = "network"; compatible = "ucc_geth"; cell-index = <3>; reg = <0x2200 0x200>; interrupts = <34>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk12"; pio-handle = <&pio3>; phy-handle = <&qe_phy2>; phy-connection-type = "rgmii-id"; }; enet1: ucc@3000 { device_type = "network"; compatible = "ucc_geth"; cell-index = <2>; reg = <0x3000 0x200>; interrupts = <33>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk17"; pio-handle = <&pio2>; phy-handle = <&qe_phy1>; phy-connection-type = "rgmii-id"; }; enet3: ucc@3200 { device_type = "network"; compatible = "ucc_geth"; cell-index = <4>; reg = <0x3200 0x200>; interrupts = <35>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "clk17"; pio-handle = <&pio4>; phy-handle = <&qe_phy3>; phy-connection-type = "rgmii-id"; }; enet5: ucc@3400 { device_type = "network"; compatible = "ucc_geth"; cell-index = <6>; reg = <0x3400 0x200>; interrupts = <41>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "none"; tbi-handle = <&tbi0>; phy-handle = <&qe_phy5>; phy-connection-type = "sgmii"; }; enet7: ucc@3600 { device_type = "network"; compatible = "ucc_geth"; cell-index = <8>; reg = <0x3600 0x200>; interrupts = <43>; interrupt-parent = <&qeic>; local-mac-address = [ 00 00 00 00 00 00 ]; rx-clock-name = "none"; tx-clock-name = "none"; tbi-handle = <&tbi1>; phy-handle = <&qe_phy7>; phy-connection-type = "sgmii"; }; muram@10000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,qe-muram", "fsl,cpm-muram"; ranges = <0x0 0x10000 0x20000>; data-only@0 { compatible = "fsl,qe-muram-data", "fsl,cpm-muram-data"; reg = <0x0 0x20000>; }; }; }; /* PCI Express */ pci1: pcie@e000a000 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0xe000a000 0x1000>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < /* IDSEL 0x0 (PEX) */ 00000 0x0 0x0 0x1 &mpic 0x0 0x1 00000 0x0 0x0 0x2 &mpic 0x1 0x1 00000 0x0 0x0 0x3 &mpic 0x2 0x1 00000 0x0 0x0 0x4 &mpic 0x3 0x1>; interrupt-parent = <&mpic>; interrupts = <26 2>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>; clock-frequency = <33333333>; pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1000000 0x0 0x0 0x0 0x800000>; }; }; rio0: rapidio@e00c00000 { #address-cells = <2>; #size-cells = <2>; compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta"; reg = <0xe00c0000 0x20000>; ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>; interrupts = <48 2 /* error */ 49 2 /* bell_outb */ 50 2 /* bell_inb */ 53 2 /* msg1_tx */ 54 2 /* msg1_rx */ 55 2 /* msg2_tx */ 56 2 /* msg2_rx */>; interrupt-parent = <&mpic>; }; }; |