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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 | /* * GE Fanuc SBC310 Device Tree Source * * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * Based on: SBS CM6 Device Tree Source * Copyright 2007 SBS Technologies GmbH & Co. KG * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) * Copyright 2006 Freescale Semiconductor Inc. */ /* * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts */ /dts-v1/; / { model = "GEF_SBC310"; compatible = "gef,sbc310"; #address-cells = <1>; #size-cells = <1>; aliases { ethernet0 = &enet0; ethernet1 = &enet1; serial0 = &serial0; serial1 = &serial1; pci0 = &pci0; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8641@0 { device_type = "cpu"; reg = <0>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <32768>; // L1, 32K i-cache-size = <32768>; // L1, 32K timebase-frequency = <0>; // From uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot }; PowerPC,8641@1 { device_type = "cpu"; reg = <1>; d-cache-line-size = <32>; // 32 bytes i-cache-line-size = <32>; // 32 bytes d-cache-size = <32768>; // L1, 32K i-cache-size = <32768>; // L1, 32K timebase-frequency = <0>; // From uboot bus-frequency = <0>; // From uboot clock-frequency = <0>; // From uboot }; }; memory { device_type = "memory"; reg = <0x0 0x40000000>; // set by uboot }; localbus@fef05000 { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8641-localbus", "simple-bus"; reg = <0xfef05000 0x1000>; interrupts = <19 2>; interrupt-parent = <&mpic>; ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 1 0 0xe0000000 0x08000000 // Paged Flash 0 2 0 0xe8000000 0x08000000 // Paged Flash 1 3 0 0xfc100000 0x00020000 // NVRAM 4 0 0xfc000000 0x00010000>; // FPGA /* flash@0,0 is a mirror of part of the memory in flash@1,0 flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x01000000>; bank-width = <2>; device-width = <2>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "firmware"; reg = <0x00000000 0x01000000>; read-only; }; }; */ flash@1,0 { compatible = "cfi-flash"; reg = <1 0 0x8000000>; bank-width = <2>; device-width = <2>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "user"; reg = <0x00000000 0x07800000>; }; partition@7800000 { label = "firmware"; reg = <0x07800000 0x00800000>; read-only; }; }; fpga@4,0 { compatible = "gef,fpga-regs"; reg = <0x4 0x0 0x40>; }; wdt@4,2000 { #interrupt-cells = <2>; device_type = "watchdog"; compatible = "gef,fpga-wdt"; reg = <0x4 0x2000 0x8>; interrupts = <0x1a 0x4>; interrupt-parent = <&gef_pic>; }; /* wdt@4,2010 { #interrupt-cells = <2>; device_type = "watchdog"; compatible = "gef,fpga-wdt"; reg = <0x4 0x2010 0x8>; interrupts = <0x1b 0x4>; interrupt-parent = <&gef_pic>; }; */ gef_pic: pic@4,4000 { #interrupt-cells = <1>; interrupt-controller; compatible = "gef,fpga-pic"; reg = <0x4 0x4000 0x20>; interrupts = <0x8 0x9>; interrupt-parent = <&mpic>; }; gef_gpio: gpio@4,8000 { #gpio-cells = <2>; compatible = "gef,sbc310-gpio"; reg = <0x4 0x8000 0x24>; gpio-controller; }; }; soc@fef00000 { #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; device_type = "soc"; compatible = "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M bus-frequency = <33333333>; i2c1: i2c@3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; interrupts = <0x2b 0x2>; interrupt-parent = <&mpic>; dfsrr; rtc@51 { compatible = "epson,rx8581"; reg = <0x00000051>; }; }; i2c2: i2c@3100 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl-i2c"; reg = <0x3100 0x100>; interrupts = <0x2b 0x2>; interrupt-parent = <&mpic>; dfsrr; hwmon@48 { compatible = "national,lm92"; reg = <0x48>; }; hwmon@4c { compatible = "adi,adt7461"; reg = <0x4c>; }; eti@6b { compatible = "dallas,ds1682"; reg = <0x6b>; }; }; dma@21300 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; reg = <0x21300 0x4>; ranges = <0x0 0x21100 0x200>; cell-index = <0>; dma-channel@0 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x0 0x80>; cell-index = <0>; interrupt-parent = <&mpic>; interrupts = <20 2>; }; dma-channel@80 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x80 0x80>; cell-index = <1>; interrupt-parent = <&mpic>; interrupts = <21 2>; }; dma-channel@100 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x100 0x80>; cell-index = <2>; interrupt-parent = <&mpic>; interrupts = <22 2>; }; dma-channel@180 { compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel"; reg = <0x180 0x80>; cell-index = <3>; interrupt-parent = <&mpic>; interrupts = <23 2>; }; }; enet0: ethernet@24000 { #address-cells = <1>; #size-cells = <1>; device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x24000 0x1000>; ranges = <0x0 0x24000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; phy-connection-type = "gmii"; mdio@520 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,gianfar-mdio"; reg = <0x520 0x20>; phy0: ethernet-phy@0 { interrupt-parent = <&gef_pic>; interrupts = <0x9 0x4>; reg = <1>; }; phy2: ethernet-phy@2 { interrupt-parent = <&gef_pic>; interrupts = <0x8 0x4>; reg = <3>; }; }; }; enet1: ethernet@26000 { device_type = "network"; model = "eTSEC"; compatible = "gianfar"; reg = <0x26000 0x1000>; local-mac-address = [ 00 00 00 00 00 00 ]; interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>; interrupt-parent = <&mpic>; phy-handle = <&phy2>; phy-connection-type = "gmii"; }; serial0: serial@4500 { cell-index = <0>; device_type = "serial"; compatible = "ns16550"; reg = <0x4500 0x100>; clock-frequency = <0>; interrupts = <0x2a 0x2>; interrupt-parent = <&mpic>; }; serial1: serial@4600 { cell-index = <1>; device_type = "serial"; compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; interrupts = <0x1c 0x2>; interrupt-parent = <&mpic>; }; mpic: pic@40000 { clock-frequency = <0>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; reg = <0x40000 0x40000>; compatible = "chrp,open-pic"; device_type = "open-pic"; }; global-utilities@e0000 { compatible = "fsl,mpc8641-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; }; pci0: pcie@fef08000 { compatible = "fsl,mpc8641-pcie"; device_type = "pci"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; reg = <0xfef08000 0x1000>; bus-range = <0x0 0xff>; ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; clock-frequency = <33333333>; interrupt-parent = <&mpic>; interrupts = <0x18 0x2>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map = < 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2 >; pcie@0 { reg = <0 0 0 0 0>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; ranges = <0x02000000 0x0 0x80000000 0x02000000 0x0 0x80000000 0x0 0x40000000 0x01000000 0x0 0x00000000 0x01000000 0x0 0x00000000 0x0 0x00400000>; }; }; }; |